Preventing glitches and short circuits in high-level self-timed chip specifications.
Stephen Longfield Jr.Brittany NkounkouRajit ManoharRoss TatePublished in: PLDI (2015)
Keyphrases
- high level
- low power
- delay insensitive
- high speed
- analog vlsi
- cmos technology
- mixed signal
- low level
- power dissipation
- low cost
- circuit design
- high bandwidth
- single chip
- chip design
- power consumption
- power reduction
- random access memory
- logic circuits
- low level features
- higher level
- shift register
- programming language
- quantum computing
- asynchronous circuits
- high density
- wide dynamic range
- source code
- analog circuits
- digital signal processing
- parallel processing
- digital circuits
- real time
- control flow
- data flow
- built in self test