Sign in
An asymmetric dual-processor architecture for low-power information appliances.
François Guimbretière
Shenwei Liu
Han Wang
Rajit Manohar
Published in:
ACM Trans. Embed. Comput. Syst. (2014)
Keyphrases
</>
low power
high speed
power consumption
wireless transmission
low cost
single chip
vlsi architecture
real time
gate array
vlsi implementation
delay insensitive