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An asymmetric dual-processor architecture for low-power information appliances.

François GuimbretièreShenwei LiuHan WangRajit Manohar
Published in: ACM Trans. Embed. Comput. Syst. (2014)
Keyphrases
  • low power
  • high speed
  • power consumption
  • wireless transmission
  • low cost
  • single chip
  • vlsi architecture
  • real time
  • gate array
  • vlsi implementation
  • delay insensitive