Sayak Ray

Publication Activity (10 Years)

Years Active: 2007-2024
Publications (10 Years): 14

Top Topics

Formal Verification

Chemical Reaction

Ibm Zenterprise

Encryption Algorithm

Top Venues

Publications

Debayan Das, Majid Sabbagh, Rana Elnaggar, Guang Chen, Sayak Ray, Jason M. Fung
Optimal Placement of TDC Sensor for Enhanced Power Side-Channel Assessment on FPGAS. VLSID (2024)
Mohammad Rahmani Fadiheh, Alex Wezel, Johannes Müller, Jörg Bormann, Sayak Ray, Jason M. Fung, Subhasish Mitra, Dominik Stoffel, Wolfgang Kunz
An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors. IEEE Trans. Computers 72 (1) (2023)
Anupam Golder, Debayan Das, Santosh Ghosh, Avinash Varna, Majid Sabbagh, Sayak Ray, Rana Elnaggar, Joseph Friel, Daniel Dinu, Jason M. Fung
Power Side-Channel Vulnerability Assessment of Lightweight Cryptographic Scheme, XOODYAK. DAC (2023)
Tobias Jauch, Alex Wezel, Mohammad Rahmani Fadiheh, Philipp Schmitz, Sayak Ray, Jason M. Fung, Christopher W. Fletcher, Dominik Stoffel, Wolfgang Kunz
Secure-by-Construction Design Methodology for CPUs: Implementing Secure Speculation on the RTL. ICCAD (2023)
Ryan Kastner, Francesco Restuccia, Andres Meza, Sayak Ray, Jason M. Fung, Cynthia Sturton
Automating hardware security property generation: invited. DAC (2022)
Mohammad Rahmani Fadiheh, Alex Wezel, Johannes Müller, Jörg Bormann, Sayak Ray, Jason M. Fung, Subhasish Mitra, Dominik Stoffel, Wolfgang Kunz
An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors. CoRR (2021)
Sujit Kumar Muduli, Pramod Subramanyan, Sayak Ray
Verification of Authenticated Firmware Load. IACR Cryptol. ePrint Arch. 2019 (2019)
Sayak Ray, Nishant Ghosh, Ramya Jayaram Masti, Arun K. Kanuparthi, Jason M. Fung
Formal Verification of Security Critical Hardware-Firmware Interactions in Commercial SoCs. DAC (2019)
Sujit Kumar Muduli, Pramod Subramanyan, Sayak Ray
Verification of Authenticated Firmware Loaders. FMCAD (2019)
Bo-Yuan Huang, Sayak Ray, Aarti Gupta, Jason M. Fung, Sharad Malik
Formal security verification of concurrent firmware in SoCs using instruction-level abstraction for hardware. DAC (2018)
Zhixing Xu, Sayak Ray, Pramod Subramanyan, Sharad Malik
Malware detection using machine learning based analysis of virtual memory access patterns. DATE (2017)
Aadithya V. Karthik, Sayak Ray, Jaijeet Roychowdhury
BEE: Predicting realistic worst case and stochastic eye diagrams by accounting for correlated bitstreams and coding strategies. ASP-DAC (2015)
Pramod Subramanyan, Yakir Vizel, Sayak Ray, Sharad Malik
Template-based Synthesis of Instruction-Level Abstractions for SoC Verification. FMCAD (2015)
Pramod Subramanyan, Sayak Ray, Sharad Malik
Evaluating the security of logic encryption algorithms. HOST (2015)
Sayak Ray, Sharad Malik
Effective abstraction for response proof of communication fabrics. NOCS (2014)
Aadithya V. Karthik, David Soloveichik, Sayak Ray, Baruch Sterin, Alan Mishchenko, Robert K. Brayton, Jaijeet Roychowdhury
NINJA: boolean modelling and formal verification of tiered-rate chemical reaction networks (extended abstract). BCB (2014)
Aadithya V. Karthik, Sayak Ray, Pierluigi Nuzzo, Alan Mishchenko, Robert K. Brayton, Jaijeet Roychowdhury
ABCD-NL: Approximating Continuous non-linear dynamical systems using purely Boolean models for analog/mixed-signal verification. ASP-DAC (2014)
Sayak Ray, Robert K. Brayton
Ranking structure in communication fabrics. MEMOCODE (2013)
Sayak Ray, Alan Mishchenko, Niklas Eén, Robert K. Brayton, Stephen Jang, Chao Chen
Mapping into LUT structures. DATE (2012)
Ansuman Banerjee, Sayak Ray, Pallab Dasgupta, P. P. Chakrabarti, S. Ramesh, P. Vignesh V. Ganesan
A dynamic assertion-based verification platform for validation of UML designs. ACM SIGSOFT Softw. Eng. Notes 37 (1) (2012)
Sayak Ray, Robert K. Brayton
Scalable progress verification in credit-based flow-control systems. DATE (2012)
Jiang Long, Sayak Ray, Baruch Sterin, Alan Mishchenko, Robert K. Brayton
Enhancing ABC for stabilization verification of SystemVerilog/VHDL models. DIFTS@FMCAD (2011)
Ansuman Banerjee, Sayak Ray, Pallab Dasgupta, Partha Pratim Chakrabarti, S. Ramesh, P. Vignesh V. Ganesan
A Dynamic Assertion-Based Verification Platform for Validation of UML Designs. ATVA (2008)
Sayak Ray, Pallab Dasgupta, P. P. Chakrabarti
A New Pseudo-Boolean Satisfiability based approach to Power Mode Schedulability Analysis. VLSI Design (2007)