Patrick Vuillod

Publication Activity (10 Years)

Years Active: 1996-2022
Publications (10 Years): 11

Top Topics

Logic Synthesis

Optimization Method

Industrial Processes

Top Venues

Publications

Walter Lau Neto, Luca G. Amarù, Vinicius Possani, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon
Improving LUT-based optimization for ASICs. DAC (2022)
Giulia Meuli, Vinicius N. Possani, Rajinder Singh, Siang-Yun Lee, Alessandro Tempia Calvino, Dewmini Sudara Marakkalage, Patrick Vuillod, Luca G. Amarù, Scott Chase, Jamil Kawa, Giovanni De Micheli
Majority-based Design Flow for AQFP Superconducting Family. DATE (2022)
Luca Gaetano Amarù, Vinicius N. Possani, Eleonora Testa, Felipe S. Marranghello, Christopher Casares, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli
LUT-Based Optimization For ASIC Design Flow. DAC (2021)
Eleonora Testa, Luca G. Amarù, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
Extending Boolean Methods for Scalable Logic Synthesis. IEEE Access 8 (2020)
Luca G. Amarù, Felipe S. Marranghello, Eleonora Testa, Christopher Casares, Vinicius N. Possani, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli
SAT-Sweeping Enhanced for Logic Synthesis. DAC (2020)
Eleonora Testa, Luca G. Amarù, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Jiong Luo, Christopher Casares, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
Scalable Boolean Methods in a Modern Synthesis Flow. DATE (2019)
Winston Haaswijk, Luca Gaetano Amarù, Patrick Vuillod, Jiong Luo, Mathias Soeken, Giovanni De Micheli
Integrated ESOP Refactoring for Industrial Designs. ICECS (2018)
Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Janet Olson, Robert K. Brayton, Giovanni De Micheli
Improvements to boolean resynthesis. DATE (2018)
Luca Gaetano Amarù, Patrick Vuillod, Jiong Luo, Janet Olson
Logic optimization and synthesis: Trends and directions in industry. DATE (2017)
Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon, Janet Olson, Robert K. Brayton, Giovanni De Micheli
Enabling exact delay synthesis. ICCAD (2017)
Luca Gaetano Amarù, Mathias Soeken, Winston Haaswijk, Eleonora Testa, Patrick Vuillod, Jiong Luo, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
Multi-level logic benchmarks: An exactness study. ASP-DAC (2017)
Luca Benini, Patrick Vuillod, Giovanni De Micheli
Iterative remapping for logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17 (10) (1998)
Patrick Vuillod, Luca Benini, Giovanni De Micheli
Re-mapping for low power under tight timing constraints. ISLPED (1997)
Patrick Vuillod, Luca Benini, Giovanni De Micheli
Generalized matching from theory to application. ICCAD (1997)
Luca Benini, Patrick Vuillod, Alessandro Bogliolo, Giovanni De Micheli
Clock Skew Optimization for Peak Current Reduction. J. VLSI Signal Process. 16 (2-3) (1997)
Patrick Vuillod, Luca Benini, Alessandro Bogliolo, Giovanni De Micheli
Clock skew optimization for peak current reduction. ISLPED (1996)
Luca Benini, Patrick Vuillod, Claudionor José Nunes Coelho Jr., Giovanni De Micheli
Synthesis of Low-Power Selectively-Clocked Systems from High-Level Specification. ISSS (1996)