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Jiong Luo
Publication Activity (10 Years)
Years Active: 2000-2022
Publications (10 Years): 9
Top Topics
Sat Solvers
Logic Synthesis
Industrial Processes
Brute Force
Top Venues
DATE
DAC
ICECS
ASP-DAC
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Publications
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Walter Lau Neto
,
Luca G. Amarù
,
Vinicius Possani
,
Patrick Vuillod
,
Jiong Luo
,
Alan Mishchenko
,
Pierre-Emmanuel Gaillardon
Improving LUT-based optimization for ASICs.
DAC
(2022)
Luca Gaetano Amarù
,
Vinicius N. Possani
,
Eleonora Testa
,
Felipe S. Marranghello
,
Christopher Casares
,
Jiong Luo
,
Patrick Vuillod
,
Alan Mishchenko
,
Giovanni De Micheli
LUT-Based Optimization For ASIC Design Flow.
DAC
(2021)
Luca G. Amarù
,
Felipe S. Marranghello
,
Eleonora Testa
,
Christopher Casares
,
Vinicius N. Possani
,
Jiong Luo
,
Patrick Vuillod
,
Alan Mishchenko
,
Giovanni De Micheli
SAT-Sweeping Enhanced for Logic Synthesis.
DAC
(2020)
Eleonora Testa
,
Luca G. Amarù
,
Mathias Soeken
,
Alan Mishchenko
,
Patrick Vuillod
,
Jiong Luo
,
Christopher Casares
,
Pierre-Emmanuel Gaillardon
,
Giovanni De Micheli
Scalable Boolean Methods in a Modern Synthesis Flow.
DATE
(2019)
Winston Haaswijk
,
Luca Gaetano Amarù
,
Patrick Vuillod
,
Jiong Luo
,
Mathias Soeken
,
Giovanni De Micheli
Integrated ESOP Refactoring for Industrial Designs.
ICECS
(2018)
Luca Gaetano Amarù
,
Mathias Soeken
,
Patrick Vuillod
,
Jiong Luo
,
Alan Mishchenko
,
Janet Olson
,
Robert K. Brayton
,
Giovanni De Micheli
Improvements to boolean resynthesis.
DATE
(2018)
Luca Gaetano Amarù
,
Patrick Vuillod
,
Jiong Luo
,
Janet Olson
Logic optimization and synthesis: Trends and directions in industry.
DATE
(2017)
Luca Gaetano Amarù
,
Mathias Soeken
,
Patrick Vuillod
,
Jiong Luo
,
Alan Mishchenko
,
Pierre-Emmanuel Gaillardon
,
Janet Olson
,
Robert K. Brayton
,
Giovanni De Micheli
Enabling exact delay synthesis.
ICCAD
(2017)
Luca Gaetano Amarù
,
Mathias Soeken
,
Winston Haaswijk
,
Eleonora Testa
,
Patrick Vuillod
,
Jiong Luo
,
Pierre-Emmanuel Gaillardon
,
Giovanni De Micheli
Multi-level logic benchmarks: An exactness study.
ASP-DAC
(2017)
Jiong Luo
,
Niraj K. Jha
Power-Efficient Scheduling for Heterogeneous Distributed Real-Time Embedded Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
26 (6) (2007)
Jiong Luo
,
Niraj K. Jha
,
Li-Shiuan Peh
Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems.
IEEE Trans. Very Large Scale Integr. Syst.
15 (4) (2007)
Le Yan
,
Jiong Luo
,
Niraj K. Jha
Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
24 (7) (2005)
Jiong Luo
,
Lin Zhong
,
Yunsi Fei
,
Niraj K. Jha
Register binding-based RTL power management for control-flow intensive designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
23 (8) (2004)
Jiong Luo
,
Niraj K. Jha
Power-profile Driven Variable Voltage Sealing for Heterogeneous Distributed Real-time Embedded Systems.
VLSI Design
(2003)
Le Yan
,
Jiong Luo
,
Niraj K. Jha
Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems.
ICCAD
(2003)
Weidong Wang
,
Tat Kee Tan
,
Jiong Luo
,
Yunsi Fei
,
Li Shang
,
Keith S. Vallerio
,
Lin Zhong
,
Anand Raghunathan
,
Niraj K. Jha
A comprehensive high-level synthesis system for control-flow intensive behaviors.
ACM Great Lakes Symposium on VLSI
(2003)
Jiong Luo
,
Li-Shiuan Peh
,
Niraj K. Jha
Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems.
DATE
(2003)
Lin Zhong
,
Jiong Luo
,
Yunsi Fei
,
Niraj K. Jha
Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors.
ICCD
(2002)
Jiong Luo
,
Niraj K. Jha
Low Power Distributed Embedded Systems: Dynamic Voltage Scaling and Synthesis.
HiPC
(2002)
Jiong Luo
,
Niraj K. Jha
Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems.
VLSI Design
(2002)
Jiong Luo
,
Niraj K. Jha
Battery-Aware Static Scheduling for Distributed Real-Time Embedded Systems.
DAC
(2001)
Jiong Luo
,
Niraj K. Jha
Power-Conscious Joint Scheduling of Periodic Task Graphs and Aperiodic Tasks in Distributed Real-Time Embedded Systems.
ICCAD
(2000)