Siang-Yun Lee

Publication Activity (10 Years)

Years Active: 2018-2024
Publications (10 Years): 14

Top Topics

Logic Synthesis

Optimization Method

Delay Insensitive

Top Venues

Publications

Rassul Bairamkulov, Siang-Yun Lee, Alessandro Tempia Calvino, Dewmini Sudara Marakkalage, Mingfei Yu, Giovanni De Micheli
Technology-Aware Logic Synthesis for Superconducting Electronics. DATE (2024)
Hanyu Wang, Siang-Yun Lee, Giovanni De Micheli
AnySyn: A Cost-Generic Logic Synthesis Framework with Customizable Cost Functions. CoRR (2023)
Siang-Yun Lee, Giovanni De Micheli
Heuristic Logic Resynthesis Algorithms at the Core of Peephole Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (11) (2023)
Siang-Yun Lee, Heinz Riener, Giovanni De Micheli
An Automated Testing and Debugging Toolkit for Gate-Level Logic Synthesis Applications. CoRR (2022)
Siang-Yun Lee, Heinz Riener, Giovanni De Micheli
Beyond local optimality of buffer and splitter insertion for AQFP circuits. DAC (2022)
Siang-Yun Lee, Heinz Riener, Alan Mishchenko, Robert K. Brayton, Giovanni De Micheli
A Simulation-Guided Paradigm for Logic Synthesis and Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (8) (2022)
Heinz Riener, Siang-Yun Lee, Alan Mishchenko, Giovanni De Micheli
Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis. ASP-DAC (2022)
Giulia Meuli, Vinicius N. Possani, Rajinder Singh, Siang-Yun Lee, Alessandro Tempia Calvino, Dewmini Sudara Marakkalage, Patrick Vuillod, Luca G. Amarù, Scott Chase, Jamil Kawa, Giovanni De Micheli
Majority-based Design Flow for AQFP Superconducting Family. DATE (2022)
Eleonora Testa, Siang-Yun Lee, Heinz Riener, Giovanni De Micheli
Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits. ASP-DAC (2021)
Siang-Yun Lee, Heinz Riener, Giovanni De Micheli
Irredundant Buffer and Splitter Insertion and Scheduling-Based Optimization for AQFP Circuits. CoRR (2021)
Siang-Yun Lee, Heinz Riener, Giovanni De Micheli
Logic Resynthesis of Majority-Based Circuits by Top-Down Decomposition. DDECS (2021)
Siang-Yun Lee, Heinz Riener, Alan Mishchenko, Robert K. Brayton, Giovanni De Micheli
Simulation-Guided Boolean Resubstitution. CoRR (2020)
Siang-Yun Lee, Nian-Ze Lee, Jie-Hong R. Jiang
Searching Parallel Separating Hyperplanes for Effective Compression of Threshold Logic Networks. ICCAD (2019)
Siang-Yun Lee, Nian-Ze Lee, Jie-Hong R. Jiang
Canonicalization of threshold logic representation and its applications. ICCAD (2018)