Paolo Camurati

Publication Activity (10 Years)

Years Active: 1986-2020
Publications (10 Years): 13

Top Topics

Logic Synthesis

Embedded Systems

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Gianpiero Cabodi, Paolo Camurati, Marco Palena, Paolo Pasini, Danilo Vendraminetto
Reducing Interpolant Circuit Size Through SAT-Based Weakening. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (7) (2020)
Gianpiero Cabodi, Paolo Camurati, Fabrizio F. Finocchiaro, Danilo Vendraminetto
Model Checking Speculation-Dependent Security Properties: Abstracting and Reducing Processor Models for Sound and Complete Verification. C2SI (2019)
Gianpiero Cabodi, Paolo Camurati, Marco Palena, Paolo Pasini, Danilo Vendraminetto
Logic Synthesis for Interpolant Circuit Compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (2) (2019)
Edoardo Fadda, Daniele Manerba, Roberto Tadei, Paolo Camurati, Gianpiero Cabodi
KPIs for Optimal Location of charging stations for Electric Vehicles: the Biella case-study. FedCSIS (2019)
Gianpiero Cabodi, Paolo Camurati, Carmelo Loiacono, Marco Palena, Paolo Pasini, Denis Patti, Stefano Quer
To split or to group: from divide-and-conquer to sub-task sharing for verifying multiple properties in model checking. Int. J. Softw. Tools Technol. Transf. 20 (3) (2018)
Gianpiero Cabodi, Paolo Camurati, Alan Mishchenko, Marco Palena, Paolo Pasini
SAT solver management strategies in IC3: an experimental approach. Formal Methods Syst. Des. 50 (1) (2017)
Gianpiero Cabodi, Paolo Camurati, Marco Palena, Paolo Pasini, Danilo Vendraminetto
Interpolation-Based Learning as a Mean to Speed-Up Bounded Model Checking (Short Paper). SEFM (2017)
Gianpiero Cabodi, Paolo Camurati, Sebastiano F. Finocchiaro, Francesco Savarese, Danilo Vendraminetto
Embedded Systems Secure Path Verification at the Hardware/Software Interface. IEEE Des. Test 34 (5) (2017)
Nicolas Boria, Gianpiero Cabodi, Paolo Camurati, Marco Palena, Paolo Pasini, Stefano Quer
A Greedy Approach to Answer Reachability Queries on DAGs. CoRR (2016)
Gianpiero Cabodi, Paolo Camurati, Marco Palena, Paolo Pasini, Danilo Vendraminetto
Reducing interpolant circuit size by ad-hoc logic synthesis and SAT-based weakening. FMCAD (2016)
Nicolas Boria, Gianpiero Cabodi, Paolo Camurati, Marco Palena, Paolo Pasini, Stefano Quer
A 7/2-Approximation Algorithm for the Maximum Duo-Preservation String Mapping Problem. CPM (2016)
Gianpiero Cabodi, Paolo Camurati, Stefano Quer
A graph-labeling approach for efficient cone-of-influence computation in model-checking problems with multiple properties. Softw. Pract. Exp. 46 (4) (2016)
Gianpiero Cabodi, Paolo Camurati, Sebastiano F. Finocchiaro, Carmelo Loiacono, Francesco Savarese, Danilo Vendraminetto
Secure Path Verification. IVSW (2016)
Gianpiero Cabodi, Paolo Camurati, Luz Garcia, Marco Murciano, Sergio Nocco, Stefano Quer
Speeding up model checking by exploiting explicit and hidden verification constraints. DATE (2009)
Gianpiero Cabodi, Paolo Camurati, Luz Garcia, Marco Murciano, Sergio Nocco, Stefano Quer
Trading-Off SAT Search and Variable Quantifications for Effective Unbounded Model Checking. FMCAD (2008)
Gianpiero Cabodi, Paolo Camurati, Marco Murciano
Automated abstraction by incremental refinement in interpolant-based model checking. ICCAD (2008)
Gianpiero Cabodi, Paolo Camurati, Stefano Quer
Can BDDs compete with SAT solvers on bounded model checking? DAC (2002)
Gianpiero Cabodi, Paolo Camurati, Stefano Quer
Dynamic Scheduling and Clustering in Symbolic Image Computation. DATE (2002)
Gianpiero Cabodi, Paolo Camurati, Stefano Quer
Reachability analysis of large circuits using disjunctive partitioning and partial iterative squaring. J. Syst. Archit. 47 (2) (2001)
Gianpiero Cabodi, Paolo Camurati, Stefano Quer
Biasing symbolic search by means of dynamic activity profiles. DATE (2001)
Gianpiero Cabodi, Paolo Camurati, Stefano Quer
Improving symbolic reachability analysis by means of activityprofiles. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (9) (2000)
Gianpiero Cabodi, Paolo Camurati, Stefano Quer
Symbolic forward/backward traversals of large finite state machines. J. Syst. Archit. 46 (12) (2000)
Stefano Quer, Gianpiero Cabodi, Paolo Camurati, Luciano Lavagno, Ellen Sentovich, Robert K. Brayton
Verification of Similar FSMs by Mixing Incremental Re-encoding, Reachability Analysis, and Combinational Checks. Formal Methods Syst. Des. 17 (2) (2000)
Gianpiero Cabodi, Paolo Camurati, Claudio Passerone, Stefano Quer
Computing Timed Transition Relations for Sequential Cycle-Based Simulation. DATE (1999)
Gianpiero Cabodi, Paolo Camurati, Stefano Quer
Improving the efficiency of BDD-based operators by means of partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (5) (1999)
Gianpiero Cabodi, Paolo Camurati, Stefano Quer
Improving Symbolic Traversals by Means of Activity Profiles. DAC (1999)
Gianpiero Cabodi, Stefano Quer, Paolo Camurati
Memory Optimization in Function and Set Manipulation with BDDs. Softw. Pract. Exp. 28 (1) (1998)
Gianpiero Cabodi, Paolo Camurati, Stefano Quer
Auxiliary variables for BDD-based representation and manipulation of Boolean functions. ACM Trans. Design Autom. Electr. Syst. 3 (3) (1998)
Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
The General Product Machine: a New Model for Symbolic FSM Traversal. Formal Methods Syst. Des. 12 (3) (1998)
Gianpiero Cabodi, Paolo Camurati, Antonio Lioy, Massimo Poncino, Stefano Quer
A parallel approach to symbolic traversal based on set partitioning. CHARME (1997)
Gianpiero Cabodi, Paolo Camurati, Luciano Lavagno, Stefano Quer
Verification and synthesis of counters based on symbolic techniques. ED&TC (1997)
Gianpiero Cabodi, Paolo Camurati, Luciano Lavagno, Stefano Quer
Disjunctive Partitioning and Partial Iterative Squaring: An Effective Approach for Symbolic Traversal of Large Circuits. DAC (1997)
Gianpiero Cabodi, Paolo Camurati
Symbolic FSM traversals based on the transition relation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (5) (1997)
Gianpiero Cabodi, Paolo Camurati, Luciano Lavagno, Stefano Quer, Robert K. Brayton, Ellen Sentovich
Incremental re-encoding for symbolic traversal of product machines. EURO-DAC (1996)
Gianpiero Cabodi, Luciano Lavagno, Enrico Macii, Massimo Poncino, Stefano Quer, Paolo Camurati, Ellen Sentovich
Enhancing FSM Traversal by Temporary Re-Encoding. ICCD (1996)
Stefano Quer, Gianpiero Cabodi, Paolo Camurati
Decomposed symbolic forward traversals of large finite state machines. EURO-DAC (1996)
Gianpiero Cabodi, Paolo Camurati, Stefano Quer
Improved reachability analysis of large finite state machines. ICCAD (1996)
Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda, Stefano Barbagallo, Andrea Burri, Davide Medina
Industrial BIST of Embedded RAMs. IEEE Des. Test Comput. 12 (3) (1995)
Gianpiero Cabodi, Stefano Quer, Paolo Camurati
Computing subsets of equivalence classes for large FSMs. EURO-DAC (1995)
Gianpiero Cabodi, Stefano Quer, Paolo Camurati
Transforming boolean relations by symbolic encoding. CHARME (1995)
Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda, Stefano Barbagallo, Andrea Burri, Davide Medina
An industrial experience in the built-in self test of embedded RAMs. VTS (1994)
Gianpiero Cabodi, Paolo Camurati, Stefano Quer
Symbolic exploration of large circuits with enhanced forward/backward traversals. EURO-DAC (1994)
Gianpiero Cabodi, Paolo Camurati, Stefano Quer
Efficient State Space Pruning in Symbolic Backward Traversal. ICCD (1994)
Gianpiero Cabodi, Paolo Camurati, Stefano Quer
Full-Symbolic ATPG for Large Circuits. ITC (1994)
Gianpiero Cabodi, Paolo Camurati, Stefano Quer
Symbolic traversals of data paths with auxiliary variables. Great Lakes Symposium on VLSI (1994)
Paolo Camurati, Fulvio Corno, Michela Meo, Paolo Prinetto
A new functional fault model for system-level descriptions. VTS (1994)
Paolo Camurati, Fulvio Corno, Paolo Prinetto, Catherine Bayol, Bernard Soulas
System-Level Modeling and Verification: a Comprehensive Design Methodology. EDAC-ETC-EUROASIC (1994)
Gianpiero Cabodi, Paolo Camurati, Stefano Quer
Auxiliary Variables for Extending Symbolic Traversal Techniques to Data Paths. DAC (1994)
Gianpiero Cabodi, Paolo Camurati, Stefano Quer
Detecting hard faults with combined approximate forward/backward symbolic techniques. ISCAS (1994)
Paolo Camurati, Fulvio Corno, Paolo Prinetto
Exploiting Symbolic Traversal Techniques for Efficient Process Algebra Manipulation. CHDL (1993)
Paolo Camurati, Fulvio Corno, Paolo Prinetto
A Methodology for System-Level Design for Verifiability. CHARME (1993)
Gianpiero Cabodi, Paolo Camurati
Exploiting Cofactoring for Efficient FSM Symbolic Traversal Based on the Transition Relation. ICCD (1993)
Paolo Camurati, Fulvio Corno, Paolo Prinetto
An efficient tool for system-level verification of behaviors and temporal properties. EURO-DAC (1993)
Gianpiero Cabodi, Paolo Camurati
Advancements in Symbolic Traversal Technique. CHARME (1993)
Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
An approach to sequential circuit diagnosis based on formal verification techniques. J. Electron. Test. 4 (1) (1993)
Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
Cross-fertilizing FSM verification techniques and sequential diagnosis. EURO-DAC (1992)
Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Silvano Gai, Paolo Prinetto, Matteo Sonza Reorda
A New Model for Improving symbolic Product Machine Traversal. DAC (1992)
Paolo Camurati, Fulvio Corno, Fulvio Prinetto, Matteo Sonza Reorda
A simulation-based approach to test pattern generation for synchronous sequential circuits. VTS (1992)
Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
Sequential Circuit Diagnosis Based on Formal Verification Techniques. ITC (1992)
Gianpiero Cabodi, Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda
TPDL: Extended Temporal Profile Description Language. Softw. Pract. Exp. 21 (4) (1991)
Paolo Camurati, Tiziana Margaria, Paolo Prinetto
Resolution-based correctness proofs of synchronous circuits. EURO-DAC (1991)
Paolo Camurati, Marco Gilli, Paolo Prinetto, Matteo Sonza Reorda
Proving finite state machines correct with an automaton-based method. Great Lakes Symposium on VLSI (1991)
Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda
Exact probabilistic testability measures for multi-output circuits. J. Electron. Test. 1 (3) (1990)
Paolo Camurati, Davide Medina, Paolo Prinetto, Matteo Sonza Reorda
A diagnostic test pattern generation algorithm. ITC (1990)
Paolo Camurati, Marco Gilli, Paolo Prinetto, Matteo Sonza Reorda
Model Checking and Graph Theory in Sequential ATPG. CAV (DIMACS/AMS volume) (1990)
Paolo Camurati, Marco Gilli, Paolo Prinetto, Matteo Sonza Reorda
The Use of Model Checking in ATPG for Sequential Circuits. CAV (1990)
Paolo Camurati, Antonio Lioy, Paolo Prinetto, Matteo Sonza Reorda
Assessing the diagnostic power of test pattern sets. Microprocessing and Microprogramming 30 (1-5) (1990)
Paolo Camurati, Tiziana Margaria, Paolo Prinetto
The OTTER environment for resolution-based proof of hardware correctness. Microprocessing and Microprogramming 30 (1-5) (1990)
Paolo Camurati, Antonio Lioy, Paolo Prinetto, Matteo Sonza Reorda
Diagnosis oriented test pattern generation. EURO-DAC (1990)
Paolo Camurati, Tiziana Margaria, Paolo Prinetto
. Microprocessing and Microprogramming 27 (1-5) (1989)
Paolo Camurati, Marco Mezzalama, Paolo Prinetto
Knowledge-based systems as an aid to computer-aided repair. Microprocess. Microsystems 13 (7) (1989)
Gianpiero Cabodi, Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda
. Microprocessing and Microprogramming 26 (4) (1989)
Dominique Borrione, Paolo Camurati, J. L. Paillet, Paolo Prinetto
A functional approach to formal hardware verification: the MTI experience. ICCD (1988)
Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda
Random testability analysis: comparing and evaluating existing approaches. ICCD (1988)
Paolo Camurati, Paolo Gianoglio, Renato Gianoglio, Paolo Prinetto
ESTA: an expert system for DFT rule verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7 (11) (1988)
Paolo Camurati, Paolo Prinetto
Formal Verification of Hardware Correctness: Introduction and Survey of Current Research. Computer 21 (7) (1988)
Gianpiero Cabodi, Paolo Camurati, Paolo Prinetto
Experiences in Prolog-Based DFT Rule Checking. FJCC (1986)