Login / Signup
Reachability analysis of large circuits using disjunctive partitioning and partial iterative squaring.
Gianpiero Cabodi
Paolo Camurati
Stefano Quer
Published in:
J. Syst. Archit. (2001)
Keyphrases
</>
reachability analysis
model checking
markov decision processes
incremental algorithms
timed automata
temporal logic
state space
high speed
reinforcement learning
datalog programs
circuit design
logic synthesis
real time
low cost
linear programming
delay insensitive