The Use of Model Checking in ATPG for Sequential Circuits.
Paolo CamuratiMarco GilliPaolo PrinettoMatteo Sonza ReordaPublished in: CAV (1990)
Keyphrases
- model checking
- temporal logic
- asynchronous circuits
- temporal properties
- formal verification
- model checker
- computation tree logic
- formal specification
- symbolic model checking
- partial order reduction
- automated verification
- pspace complete
- finite state
- process algebra
- timed automata
- reachability analysis
- bounded model checking
- epistemic logic
- formal methods
- verification method
- finite state machines
- reactive systems
- linear temporal logic
- transition systems
- satisfiability problem
- alternating time temporal logic
- artificial intelligence