Dominique Borrione

ORCID

Publication Activity (10 Years)

Years Active: 1980-2019
Publications (10 Years): 7

Top Venues

VLSI-SoC

FDL

MEMOCODE

ACM Trans. Embed. Comput. Syst.

Grenoble Institute of Technology, France (PHD)

Education History

Grenoble Institute of Technology, France

PHD

Publications

Guillaume Plassan, Katell Morin-Allory, Dominique Borrione
Mining Missing Assumptions from Counter-Examples. ACM Trans. Embed. Comput. Syst. 18 (1) (2019)
Fatemeh Negin Javaheri, Katell Morin-Allory, Dominique Borrione
Synthesis of Regular Expressions Revisited: From PSL SEREs to Hardware. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (5) (2017)
Guillaume Plassan, Katell Morin-Allory, Dominique Borrione
Extraction of missing formal assumptions in under-constrained designs. MEMOCODE (2017)
Guillaume Plassan, Hans-Jörg Peter, Katell Morin-Allory, Shaker Sarwary, Dominique Borrione
Improving the Efficiency of Formal Verification: The Case of Clock-Domain Crossings. VLSI-SoC (Selected Papers) (2016)
Guillaume Plassan, Hans-Jörg Peter, Katell Morin-Allory, Fahim Rahim, Shaker Sarwary, Dominique Borrione
Conclusively verifying clock-domain crossings in very large hardware designs. VLSI-SoC (2016)
Katell Morin-Allory, Fatemeh Negin Javaheri, Dominique Borrione
Efficient and Correct by Construction Assertion-Based Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 23 (12) (2015)
Mejid Kebaili, Katell Morin-Allory, Jean-Christophe Brignone, Dominique Borrione
Enabler-based synchronizer model for clock domain crossing static verification. FDL (2015)
Zeineb Bel Hadj Amor, Laurence Pierre, Dominique Borrione
A tool for the automatic TLM-to-RTL conversion of embedded systems requirements for a seamless verification flow. VLSI-SoC (2014)
Dominique Borrione, Ashraf M. Salem
Application of formal methods for design space exploration and refinement. FDL (2013)
Katell Morin-Allory, Fatemeh Negin Javaheri, Dominique Borrione
SyntHorus-2: Automatic prototyping from PSL. VLSI-SoC (2013)
Katell Morin-Allory, Fatemeh Negin Javaheri, Dominique Borrione
Fast prototyping from assertions: A pragmatic approach. MEMOCODE (2013)
Katell Morin-Allory, Marc Boule, Dominique Borrione, Zeljko Zilic
Validating Assertion Language Rewrite Rules and Semantics With Automated Theorem Provers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (9) (2010)
Yann Oddos, Katell Morin-Allory, Dominique Borrione
From Assertion-Based Verification to Assertion-Based Synthesis. VLSI-SoC (2009)
Dominique Borrione, Amr Helmy, Laurence Pierre, Julien Schmaltz
A Formal Approach to the Verification of Networks on Chip. EURASIP J. Embed. Syst. 2009 (2009)
Yann Oddos, Katell Morin-Allory, Dominique Borrione, Marc Boule, Zeljko Zilic
MYGEN: automata-based on-line test generator for assertion-based verification. ACM Great Lakes Symposium on VLSI (2009)
Florent Ouchet, Dominique Borrione, Katell Morin-Allory, Laurence Pierre
High-level symbolic simulation for automatic model extraction. DDECS (2009)
Yann Oddos, Katell Morin-Allory, Dominique Borrione
Assertion-Based Design with Horus. MEMOCODE (2008)
Katell Morin-Allory, Marc Boule, Dominique Borrione, Zeljko Zilic
Proving and disproving assertion rewrite rules with automated theorem provers. HLDVT (2008)
Julien Schmaltz, Dominique Borrione
A functional formalization of on chip communications. Formal Aspects Comput. 20 (3) (2008)
Dominique Borrione, Amr Helmy, Laurence Pierre, Julien Schmaltz
Executable formal specification and validation of NoC communication infrastructures. SBCCI (2008)
Dominique Borrione, Amr Helmy, Laurence V. Pierre, Julien Schmaltz
A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study. NOCS (2007)
Katell Morin-Allory, Eric Gascard, Dominique Borrione
Synthesis of Property Monitors for Online Fault Detection. J. Circuits Syst. Comput. 16 (6) (2007)
Yann Oddos, Katell Morin-Allory, Dominique Borrione
Prototyping Generators for On-line Test Vector Generation Based on PSL Properties. DDECS (2007)
Katell Morin-Allory, Laurent Fesquet, Benjamin Roustan, Dominique Borrione
Asynchronous online-monitoring of logical and temporal assertions. FDL (2007)
Katell Morin-Allory, Dominique Borrione
On-line Monitoring of Properties Built on Regular Expressions. FDL (2006)
Katell Morin-Allory, Laurent Fesquet, Dominique Borrione
Asynchronous Assertion Monitors for multi-Clock Domain System Verification. IEEE International Workshop on Rapid System Prototyping (2006)
Julien Schmaltz, Dominique Borrione
Formalizing On Chip Communications in a Functional Style. Trustworthy Software (2006)
Julien Schmaltz, Dominique Borrione
Towards a formal theory of on chip communications in the ACL2 logic. ACL2 (2006)
Yann Oddos, Katell Morin-Allory, Dominique Borrione
On-Line Test Vector Generation from Temporal Constraints Written in PSL. VLSI-SoC (2006)
Katell Morin-Allory, Dominique Borrione
Proven correct monitors from PSL specifications. DATE (2006)
Ghiath Al Sammane, Dominique Borrione, Remy Chevallier
Verification of behavioral descriptions by combining symbolic simulation and automatic reasoning. ACM Great Lakes Symposium on VLSI (2005)
Julien Schmaltz, Dominique Borrione
A Generic Network on Chip Model. TPHOLs (2005)
Katell Morin-Allory, Dominique Borrione
A proof of correctness for the construction of property monitors. HLDVT (2005)
Diana Toma, Dominique Borrione
Formal Verification of a SHA-1 Circuit Core Using ACL2. TPHOLs (2005)
Diana Toma, Dominique Borrione, Ghiath Al Sammane
Combining Several Paradigms for Circuit Validation and Verification. CASSIS (2004)
Ghiath Al Sammane, Julien Schmaltz, Diana Toma, Pierre Ostier, Dominique Borrione
TheoSim: combining symbolic simulation and theorem proving for hardware verification. SBCCI (2004)
Julien Schmaltz, Dominique Borrione
A Functional Approach to the Formal Specification of Networks on Chip. FMCAD (2004)
Emil Dumitrescu, Dominique Borrione
Symbolic Simulation as a Simplifying Strategy for SoC Verification. IWSOC (2003)
Dominique Borrione, Menouer Boubekeur, Laurent Mounier, Marc Renaudin, Antoine Siriani
Validation of asynchronous circuit specifications using IF/CADP. VLSI-SOC (2003)
Ghiath Al Sammane, Diana Toma, Julien Schmaltz, Pierre Ostier, Dominique Borrione
Constrained Symbolic Simulation with Mathematica and ACL2. CHARME (2003)
Dominique Borrione, Menouer Boubekeur, Emil Dumitrescu, Marc Renaudin, Jean-Baptiste Rigaud, Antoine Siriani
An Approach to the Introduction of Formal Validation in an Asynchronous Circuit Design Flow. HICSS (2003)
Dominique Borrione, Menouer Boubekeur, Laurent Mounier, Marc Renaudin, Antoine Siriani
Validation of Asynchronous Circuit Specifications Using IF/CADP. VLSI-SoC (Selected Papers) (2003)
Dominique Borrione, Menouer Boubekeur
Modeling CHP descriptions in Labeled Transitions Systems for an efficient formal validation of asynchronous circuit specifications. FDL (2003)
Joel Blasquez, Marten van Hulst, Andrea Fedeli, Jean-Luc Lambert, Dominique Borrione, Coby Hanoch, Pierre Bricaud
Formal Verification Techniques: Industrial Status and Perspectives. DATE (2002)
Jorgiano Vidal, David Déharbe, Dominique Borrione
Improving Static Ordering of BDDs for Reachability Analysis. IWLS (2002)
Sherief Reda, Ayman Wahba, Ashraf Salem, Dominique Borrione, M. Ghonaimy
On the use of don't cares during symbolic reachability analysis. ISCAS (5) (2001)
Vanderlei Moraes Rodrigues, Dominique Borrione, Philippe Georgelin
An ACL2 Model of VHDL for Symbolic Simulation and Formal Verification. SBCCI (2000)
Vanderlei Moraes Rodrigues, Dominique Borrione, Philippe Georgelin
Using the ACL2 Theorem Prover to Reason about VHDL Components. RITA 7 (1) (2000)
Dominique Borrione, Julia Dushina, Laurence V. Pierre
A compositional model for the functional verification of high-level synthesis results. IEEE Trans. Very Large Scale Integr. Syst. 8 (5) (2000)
Raimund Ubar, Dominique Borrione
Design Error Diagnosis in Digital Circuits without Error Model. VLSI (1999)
Dominique Borrione, Julia Dushina, Laurence Pierre
Formalization of Finite State Machines with Data Path for the Verification of High-Level Synthesis. SBCCI (1998)
Raimund Ubar, Dominique Borrione
Generation of Tests for the Localization of Single Gate Design Errors in Combinational Circuits using the Stuck-at Fault Model. SBCCI (1998)
Ayman M. Wahba, Dominique Borrione
Connection error location and correction in combinational circuits. ED&TC (1997)
Dominique Borrione, F. Vestman, H. Bouamama
An approach to Verilog-VHDL interoperability for synchronous designs. CHARME (1997)
Ayman M. Wahba, Dominique Borrione
Automatic diagnosis may replace simulation for correcting simple design errors. EURO-DAC (1996)
Dominique Borrione, H. Bouamama, David Déharbe, C. Le Faou, Ayman M. Wahba
HDL-Based Integration of Formal Methods and CAD Tools in the PREVAIL Environment. FMCAD (1996)
Ayman M. Wahba, Dominique Borrione
A method for automatic design error location and correction in combinational logic circuits. J. Electron. Test. 8 (2) (1996)
Dominique Borrione, Ashraf M. Salem
Denotational Semantics of a Synchronous VHDL Subset. Formal Methods Syst. Des. 7 (1/2) (1995)
David Déharbe, Dominique Borrione
Semantics of a verification-oriented subset of VHDL. CHARME (1995)
Ayman M. Wahba, Dominique Borrione
Design error diagnosis in sequential circuits. CHARME (1995)
Catherine Bayol, Bernard Soulas, Dominique Borrione, Fulvio Corno, Paolo Prinetto
A process algebra interpretation of a verification oriented overlanguage of VHDL. EURO-DAC (1994)
Dominique Borrione, Robert Piloty, Dwight D. Hill, Karl J. Lieberherr, Philip Moorby
Three Decades of HDLs: Part II, Conlan Through Verilog. IEEE Des. Test Comput. 9 (3) (1992)
Dominique Borrione, Laurence V. Pierre, Ashraf M. Salem
Formal Verification of VHDL Descriptions in the Prevail Environment. IEEE Des. Test Comput. 9 (2) (1992)
Dominique Borrione, Paolo Prinetto
Zero-Defect Designs, Why and How: Formal Verification vs. Automated Synthesis. IFIP Congress (1989)
Dominique Borrione, Paolo Camurati, J. L. Paillet, Paolo Prinetto
A functional approach to formal hardware verification: the MTI experience. ICCD (1988)
Robert Piloty, Dominique Borrione
The conlan project: Status and future plans. DAC (1982)
Robert Piloty, Mario Barbacci, Dominique Borrione, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly
CONLAN: a formal construction method for hardware description languages: basic principles. AFIPS National Computer Conference (1980)
Robert Piloty, Mario Barbacci, Dominique Borrione, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly
CONLAN: a formal construction method for hardware description languages: language application. AFIPS National Computer Conference (1980)
Robert Piloty, Mario Barbacci, Dominique Borrione, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly
An Overview of CONLAN: A Formal Construction Method for Hardware Description Language. IFIP Congress (1980)
Robert Piloty, Mario Barbacci, Dominique Borrione, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly
CONLAN: a formal construction method for hardware description languages: language derivation. AFIPS National Computer Conference (1980)

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Publication Activity (10 Years)

Top Topics

Top Venues

Dominique Borrione