Login / Signup
A process algebra interpretation of a verification oriented overlanguage of VHDL.
Catherine Bayol
Bernard Soulas
Dominique Borrione
Fulvio Corno
Paolo Prinetto
Published in:
EURO-DAC (1994)
Keyphrases
</>
process algebra
concurrent systems
model checking
asynchronous circuits
formal methods
formal specification
grid workflow
temporal logic
concurrent programs
distributed systems
petri net
web services composition
high level
protocol specification
communication protocols
fine grained
artificial intelligence