Marc Boule

Publication Activity (10 Years)

Years Active: 2002-2016
Publications (10 Years): 1

Top Topics

Symbolic Execution

Simulation Data

Quality Assurance

Mutation Testing

Top Venues

ACM Trans. Design Autom. Electr. Syst.

Publications

Jason G. Tong, Marc Boule, Zeljko Zilic
Accelerating assertion assessment using GPUs. HLDVT (2016)
Jason G. Tong, Marc Boule, Zeljko Zilic
Test compaction techniques for assertion-based test generation. ACM Trans. Design Autom. Electr. Syst. 19 (1) (2013)
Jason G. Tong, Marc Boule, Zeljko Zilic
Efficient Data Encoding for Improving Fault Simulation Performance on GPUs. ISED (2013)
Katell Morin-Allory, Marc Boule, Dominique Borrione, Zeljko Zilic
Validating Assertion Language Rewrite Rules and Semantics With Automated Theorem Provers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (9) (2010)
Jason G. Tong, Marc Boule, Zeljko Zilic
Defining and Providing Coverage for Assertion-Based Dynamic Verification. J. Electron. Test. 26 (2) (2010)
Jason G. Tong, Marc Boule, Zeljko Zilic
Airwolf-TG: A test generator for assertion-based dynamic verification. HLDVT (2009)
Yann Oddos, Katell Morin-Allory, Dominique Borrione, Marc Boule, Zeljko Zilic
MYGEN: automata-based on-line test generator for assertion-based verification. ACM Great Lakes Symposium on VLSI (2009)
Katell Morin-Allory, Marc Boule, Dominique Borrione, Zeljko Zilic
Proving and disproving assertion rewrite rules with automated theorem provers. HLDVT (2008)
Marc Boule, Zeljko Zilic
Automata-based assertion-checker synthesis of PSL properties. ACM Trans. Design Autom. Electr. Syst. 13 (1) (2008)
Marc Boule, Jean-Samuel Chenard, Zeljko Zilic
Debug enhancements in assertion-checker generation. IET Comput. Digit. Tech. 1 (6) (2007)
Marc Boule, Zeljko Zilic
Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation. ASP-DAC (2007)
Marc Boule, Jean-Samuel Chenard, Zeljko Zilic
Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis. ISQED (2007)
Marc Boule, Jean-Samuel Chenard, Zeljko Zilic
Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug. ICCD (2006)
Marc Boule, Zeljko Zilic
Efficient Automata-Based Assertion-Checker Synthesis of PSL Properties. HLDVT (2006)
Marc Boule, Zeljko Zilic
Incorporating Ef.cient Assertion Checkers into Hardware Emulation. ICCD (2005)
Marc Boule, Zeljko Zilic
An FPGA Move Generator for the Game of Chess. J. Int. Comput. Games Assoc. 25 (2) (2002)
Marc Boule, Zeljko Zilic
An FPGA based move generator for the game of chess. CICC (2002)