A Formal Approach to the Verification of Networks on Chip.
Dominique BorrioneAmr HelmyLaurence PierreJulien SchmaltzPublished in: EURASIP J. Embed. Syst. (2009)
Keyphrases
- high bandwidth
- formal methods
- functional verification
- high speed
- formal analysis
- low cost
- complex networks
- formal model
- heterogeneous networks
- signature verification
- real time
- network structure
- data sets
- network model
- network analysis
- end to end
- telecommunication networks
- single chip
- network topologies
- wireless sensor networks
- programmable logic
- verification method