Matheus T. Moreira

Publication Activity (10 Years)

Years Active: 2008-2021
Publications (10 Years): 28

Top Topics

Asynchronous Circuits

Mutual Exclusion

Top Venues

Publications

Walter Lau Neto, Matheus T. Moreira, Yingjie Li, Luca G. Amarù, Cunxi Yu, Pierre-Emmanuel Gaillardon
SLAP: A Supervised Learning Approach for Priority Cuts Technology Mapping. DAC (2021)
Leonardo Rezende Juracy, Matheus T. Moreira, Alexandre M. Amory, Fernando Gehm Moraes
A TensorFlow and System Simulator Integration Approach to Estimate Hardware Metrics of Convolution Accelerators. LASCAS (2021)
Taciano A. Rodolfo, Marcos L. L. Sartori, Matheus T. Moreira, Ney Laert Vilar Calazans
Quasi Delay Insensitive FIFOs: Design Choices Exploration and Comparison. ISCAS (2021)
Marcos L. L. Sartori, Rodrigo N. Wuerdig, Matheus T. Moreira, Sergio Bampi, Ney Laert Vilar Calazans
Leveraging QDI Robustness to Simplify the Design of IoT Circuits. ISCAS (2020)
Felipe A. Kuentzer, Leonardo Rezende Juracy, Matheus T. Moreira, Alexandre M. Amory
Test Oriented Design and Layout Generation of an Asynchronous Controller for the Blade Template. ASYNC (2020)
Marcos L. L. Sartori, Matheus T. Moreira, Ney Laert Vilar Calazans
A Frontend using Traditional EDA Tools for the Pulsar QDI Design Flow. ASYNC (2020)
Marcos L. L. Sartori, Rodrigo N. Wuerdig, Matheus T. Moreira, Ney Laert Vilar Calazans
Pulsar: Constraining QDI Circuits Cycle Time Using Traditional EDA Tools. ASYNC (2019)
Leonardo Rezende Juracy, Matheus T. Moreira, Felipe A. Kuentzer, Alexandre M. Amory
A DfT Insertion Methodology to Scannable Q-Flop Elements. IEEE Trans. Very Large Scale Integr. Syst. 26 (8) (2018)
Felipe A. Kuentzer, Leonardo Rezende Juracy, Matheus T. Moreira, Alexandre M. Amory
Testable Error Detection Logic Design Applied to an Asynchronous Timing Resilient Template. SBCCI (2018)
Leonardo Rezende Juracy, Matheus T. Moreira, Felipe A. Kuentzer, Fernando Gehm Moraes, Alexandre M. Amory
An LSSD Compliant Scan Cell for Flip-Flops. ISCAS (2018)
Matheus T. Moreira, Peter A. Beerel, Marcos L. L. Sartori, Ney Laert Vilar Calazans
NCL Synthesis With Conventional EDA Tools: Technology Mapping and Optimization. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2018)
Maicon Schneider Cardoso, Gustavo H. Smaniotto, Andrei A. O. Bubolz, Matheus T. Moreira, Leomar S. da Rosa Jr., Felipe de Souza Marques
Libra: An Automatic Design Methodology for CMOS Complex Gates. IEEE Trans. Circuits Syst. II Express Briefs (10) (2018)
Gustavo H. Smaniotto, Regis Zanandrea, Maicon Schneider Cardoso, Renato Souza de Souza, Matheus T. Moreira, Felipe S. Marques, Leomar S. da Rosa Jr.
A post-processing methodology to improve the automatic design of CMOS gates at layout-level. ICECS (2017)
Leandro S. Heck, Matheus T. Moreira, Ney Laert Vilar Calazans
Hardening C-elements against metastability. ICECS (2017)
Felipe T. Bortolon, Fernando Gehm Moraes, Matheus T. Moreira, Sergio Bampi
Estimation methods for static noise margins in CMOS subthreshold logic circuits. SBCCI (2017)
Ricardo A. Guazzelli, Matheus T. Moreira, Ney Laert Vilar Calazans
A comparison of asynchronous QDI templates using static logic. LASCAS (2017)
Ricardo A. Guazzelli, Matheus T. Moreira, Walter Lau Neto, Ney Laert Vilar Calazans
Sleep convention logic isochronic fork: an analysis. SBCCI (2017)
Maicon Schneider Cardoso, Gustavo H. Smaniotto, Joao J. da S. Machado, Matheus T. Moreira, Leomar S. da Rosa, Felipe de Souza Marques
Transistor placement strategies for non-series-parallel cells. MWSCAS (2017)
Gustavo H. Smaniotto, Regis Zanandrea, Maicon Schneider Cardoso, Renato Souza de Souza, Matheus T. Moreira, Felipe S. Marques, Leomar S. da Rosa Jr.
Post-processing of supergate networks aiming cell layout optimization. ISCAS (2017)
Sergio Johann Filho, Matheus T. Moreira, Leandro S. Heck, Ney Laert Vilar Calazans, Fabiano Passuelo Hessel
A processor for IoT applications: An assessment of design space and trade-offs. Microprocess. Microsystems 42 (2016)
Ramy N. Tadros, Weizhe Hua, Matheus T. Moreira, Ney Laert Vilar Calazans, Peter A. Beerel
A Low-Power Low-Area Error-Detecting Latch for Resilient Architectures in 28-nm FDSOI. IEEE Trans. Circuits Syst. II Express Briefs (9) (2016)
Ajay Singhvi, Matheus T. Moreira, Ramy N. Tadros, Ney Laert Vilar Calazans, Peter A. Beerel
A Fine-Grain, Uniform, Energy-Efficient Delay Element for 2-Phase Bundled-Data Circuits. ACM J. Emerg. Technol. Comput. Syst. 13 (2) (2016)
Carlos Henrique Menezes Oliveira, Matheus T. Moreira, Ricardo A. Guazzelli, Ney Laert Vilar Calazans
ASCEnD-FreePDK45: An open source standard cell library for asynchronous design. ICECS (2016)
Yang Zhang, Leandro S. Heck, Matheus T. Moreira, David Zar, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel
Testable MUTEX Design. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2016)
Ramy N. Tadros, Weizhe Hua, Matheus Gibiluka, Matheus T. Moreira, Ney Laert Vilar Calazans, Peter A. Beerel
Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications. ASYNC (2016)
Sergio Johann Filho, Matheus T. Moreira, Ney Laert Vilar Calazans, Fabiano Passuelo Hessel
The HF-RISC processor: Performance assessment. LASCAS (2016)
Gustavo H. Smaniotto, Joao J. da S. Machado, Matheus T. Moreira, Adriel Mota Ziesemer, Felipe S. Marques, Leomar S. da Rosa Jr.
Optimizing cell area by applying an alternative transistor folding technique in an open source physical synthesis CAD tool. LASCAS (2016)
Gustavo H. Smaniotto, Matheus T. Moreira, Adriel Mota Ziesemer, Felipe S. Marques, Leomar S. da Rosa
Toward better layout design in ASTRAN CAD tool by using an efficient transistor folding. MWSCAS (2016)
Ajay Singhvi, Matheus T. Moreira, Ramy N. Tadros, Ney Laert Vilar Calazans, Peter A. Beerel
A Fine-Grained, Uniform, Energy-Efficient Delay Element for FD-SOI Technologies. ISVLSI (2015)
Guilherme Heck, Leandro S. Heck, Matheus T. Moreira, Fernando Gehm Moraes, Ney Laert Vilar Calazans
A digitally controlled oscillator for fine-grained local clock generators in MPSoCs. LASCAS (2015)
Guilherme Heck, Leandro S. Heck, Ajay Singhvi, Matheus T. Moreira, Peter A. Beerel, Ney Laert Vilar Calazans
Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits. VLSI Design (2015)
Ricardo A. Guazzelli, Fernando Gehm Moraes, Ney Laert Vilar Calazans, Matheus T. Moreira
SDDS-NCL Design: Analysis of Supply Voltage Scaling. SBCCI (2015)
Yang Zhang, Leandro S. Heck, Matheus T. Moreira, David Zar, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel
Design and Analysis of Testable Mutual Exclusion Elements. ASYNC (2015)
Matheus T. Moreira, Dylan Hand, Peter A. Beerel, Ney Laert Vilar Calazans
TDTB error detecting latches: Timing violation sensitivity analysis and optimization. ISQED (2015)
Matheus T. Moreira, Ney Laert Vilar Calazans
Advances on the state of the art in QDI design. VLSI-SoC (2014)
Matheus T. Moreira, Augusto Neutzling, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas, Ney Calazans
Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible? ASYNC (2014)
Adriel Ziesemer, Ricardo Reis, Matheus T. Moreira, Michel Evandro Arendt, Ney Laert Vilar Calazans
Automatic layout synthesis with ASTRAN applied to asynchronous cells. LASCAS (2014)
Adriel Ziesemer, Ricardo Reis, Matheus T. Moreira, Michel Evandro Arendt, Ney Laert Vilar Calazans
A design flow for physical synthesis of digital cells with ASTRAN. ACM Great Lakes Symposium on VLSI (2014)
Matheus T. Moreira, Julian J. H. Pontes, Ney Laert Vilar Calazans
Tradeoffs between RTO and RTZ in WCHB QDI asynchronous design. ISQED (2014)
Ricardo A. Guazzelli, Guilherme Heck, Matheus T. Moreira, Ney Laert Vilar Calazans
Schmitt trigger on output inverters of NCL gates for soft error hardening: Is it enough? LATW (2014)
Matheus T. Moreira, Felipe G. Magalhaes, Matheus Gibiluka, Fabiano Hessel, Ney Laert Vilar Calazans
BaBaNoC: An asynchronous network-on-chip described in Balsa. RSP (2013)
Alexandre M. Amory, Matheus T. Moreira, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Cristiano Lazzari, Marcelo Soares Lubaszewski
Evaluating the scalability of test buses. ISSoC (2013)
Matheus T. Moreira, Carlos Henrique Menezes Oliveira, Ricardo C. Porto, Ney Laert Vilar Calazans
NCL+: Return-to-one Null Convention Logic. MWSCAS (2013)
Yan Ghidini, Matheus T. Moreira, Lucas Brahm, Thais Webber, Ney Calazans, César A. M. Marcon
Lasio 3D NoC vertical links serialization: Evaluation of latency and buffer occupancy. SBCCI (2013)
Matheus T. Moreira, Bruno S. Oliveira, Fernando Gehm Moraes, Ney Laert Vilar Calazans
Charge sharing aware NCL gates design. DFTS (2013)
Matheus T. Moreira, Carlos Henrique Menezes Oliveira, Ricardo C. Porto, Ney Laert Vilar Calazans
Design of NCL gates with the ASCEnD flow. LASCAS (2013)
Matheus T. Moreira, Ney Laert Vilar Calazans
Electrical characterization of a C-Element with LiChEn. ICECS (2012)
Matheus T. Moreira, Bruno Cruz de Oliveira, Fernando Moraes, Ney Calazans
Impact of C-elements in asynchronous circuits. ISQED (2012)
Matheus T. Moreira, Ricardo A. Guazzelli, Ney Laert Vilar Calazans
Return-to-One DIMS logic on 4-phase m-of-n asynchronous circuits. ICECS (2012)
Fernando Gehm Moraes, Matheus T. Moreira, Carlos Lucas, D. Correa, Douglas de O. Cardoso, M. Magnaguagno, Guilherme M. Castilhos, Ney Laert Vilar Calazans
A generic FPGA emulation framework. ICECS (2012)
Matheus T. Moreira, Ricardo A. Guazzelli, Ney Laert Vilar Calazans
Return-to-one protocol for reducing static power in C-elements of QDI circuits employing m-of-n codes. SBCCI (2012)
Matheus T. Moreira, Bruno Cruz de Oliveira, Julian J. H. Pontes, Fernando Moraes, Ney Calazans
Adapting a C-element design flow for low power. ICECS (2011)
Matheus T. Moreira, Bruno Cruz de Oliveira, Julian J. H. Pontes, Ney Calazans
A 65nm standard cell set and flow dedicated to automated asynchronous circuits design. SoCC (2011)
Julian J. H. Pontes, Matheus T. Moreira, Fernando Moraes, Ney Calazans
Hermes-AA: A 65nm asynchronous NoC router with adaptive routing. SoCC (2010)
Julian J. H. Pontes, Matheus T. Moreira, Fernando Moraes, Ney Calazans
Hermes-A - An Asynchronous NoC Router with Distributed Routing. PATMOS (2010)
Julian J. H. Pontes, Matheus T. Moreira, Rafael Soares, Ney Laert Vilar Calazans
Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques. ISVLSI (2008)