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A Low-Power Low-Area Error-Detecting Latch for Resilient Architectures in 28-nm FDSOI.
Ramy N. Tadros
Weizhe Hua
Matheus T. Moreira
Ney Laert Vilar Calazans
Peter A. Beerel
Published in:
IEEE Trans. Circuits Syst. II Express Briefs (2016)
Keyphrases
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low power
power consumption
cmos technology
low power consumption
low cost
high speed
power reduction
nm technology
single chip
high power
wireless transmission
digital signal processing
logic circuits
power dissipation
vlsi architecture
gate array
mixed signal
power saving
signal processing