Weizhe Hua

Publication Activity (10 Years)

Years Active: 2016-2024
Publications (10 Years): 27

Top Topics

Information Flow

Reverse Engineer

Top Venues

Publications

Trishita Tiwari, Suchin Gururangan, Chuan Guo, Weizhe Hua, Sanjay Kariyappa, Udit Gupta, Wenjie Xiong, Kiwan Maeng, Hsien-Hsin S. Lee, G. Edward Suh
Information Flow Control in Machine Learning through Modular Model Architecture. USENIX Security Symposium (2024)
Trishita Tiwari, Suchin Gururangan, Chuan Guo, Weizhe Hua, Sanjay Kariyappa, Udit Gupta, Wenjie Xiong, Kiwan Maeng, Hsien-Hsin S. Lee, G. Edward Suh
Information Flow Control in Machine Learning through Modular Model Architecture. CoRR (2023)
Weizhe Hua, Zhiru Zhang, G. Edward Suh
Reverse-Engineering CNN Models Using Side-Channel Attacks. IEEE Des. Test 39 (4) (2022)
Weizhe Hua, Zihang Dai, Hanxiao Liu, Quoc V. Le
Transformer Quality in Linear Time. CoRR (2022)
Muhammad Umar, Weizhe Hua, Zhiru Zhang, G. Edward Suh
SoftVN: efficient memory protection via software-provided version numbers. ISCA (2022)
Weizhe Hua, Muhammad Umar, Zhiru Zhang, G. Edward Suh
MGX: near-zero overhead memory protection for data-intensive accelerators. ISCA (2022)
Weizhe Hua, Muhammad Umar, Zhiru Zhang, G. Edward Suh
GuardNN: secure accelerator architecture for privacy-preserving deep learning. DAC (2022)
Weizhe Hua, Zihang Dai, Hanxiao Liu, Quoc V. Le
Transformer Quality in Linear Time. ICML (2022)
Yaohui Cai, Weizhe Hua, Hongzheng Chen, G. Edward Suh, Christopher De Sa, Zhiru Zhang
Structured Pruning is All You Need for Pruning CNNs at Initialization. CoRR (2022)
Weizhe Hua, Yichi Zhang, Chuan Guo, Zhiru Zhang, G. Edward Suh
BulletTrain: Accelerating Robust Neural Network Training via Boundary Example Mining. CoRR (2021)
Yanqi Zhang, Weizhe Hua, Zhuangzhuang Zhou, Ed Suh, Christina Delimitrou
Sinan: Data Driven Resource Management for Cloud Microservices. CoRR (2021)
Yanqi Zhang, Weizhe Hua, Zhuangzhuang Zhou, G. Edward Suh, Christina Delimitrou
Sinan: Data-Driven, QoS-Aware Cluster Management for Microservices. CoRR (2021)
Yanqi Zhang, Weizhe Hua, Zhuangzhuang Zhou, G. Edward Suh, Christina Delimitrou
Sinan: ML-based and QoS-aware resource management for cloud microservices. ASPLOS (2021)
Weizhe Hua, Yichi Zhang, Chuan Guo, Zhiru Zhang, G. Edward Suh
BulletTrain: Accelerating Robust Neural Network Training via Boundary Example Mining. NeurIPS (2021)
Weizhe Hua, Muhammad Umar, Zhiru Zhang, G. Edward Suh
GuardNN: Secure DNN Accelerator for Privacy-Preserving Deep Learning. CoRR (2020)
Yichi Zhang, Ritchie Zhao, Weizhe Hua, Nayun Xu, G. Edward Suh, Zhiru Zhang
Precision Gating: Improving Neural Network Efficiency with Dynamic Dual-Precision Activations. CoRR (2020)
Yichi Zhang, Ritchie Zhao, Weizhe Hua, Nayun Xu, G. Edward Suh, Zhiru Zhang
Precision Gating: Improving Neural Network Efficiency with Dynamic Dual-Precision Activations. ICLR (2020)
Weizhe Hua, Muhammad Umar, Zhiru Zhang, G. Edward Suh
MgX: Near-Zero Overhead Memory Protection with an Application to Secure DNN Acceleration. CoRR (2020)
Qiwei Yuan, Weizhe Hua, Yi Zhou, Cunxi Yu
Contrastive Weight Regularization for Large Minibatch SGD. CoRR (2020)
Weizhe Hua, Yuan Zhou, Christopher De Sa, Zhiru Zhang, G. Edward Suh
Channel Gating Neural Networks. NeurIPS (2019)
Weizhe Hua, Yuan Zhou, Christopher De Sa, Zhiru Zhang, G. Edward Suh
Boosting the Performance of CNN Accelerators with Dynamic Fine-Grained Channel Gating. MICRO (2019)
Weizhe Hua, Christopher De Sa, Zhiru Zhang, G. Edward Suh
Channel Gating Neural Networks. CoRR (2018)
Weizhe Hua, Zhiru Zhang, G. Edward Suh
Reverse engineering convolutional neural networks through side-channel information leaks. DAC (2018)
Andrew Ferraiuolo, Weizhe Hua, Andrew C. Myers, G. Edward Suh
Secure Information Flow Verification with Mutable Dependent Types. DAC (2017)
Weizhe Hua, Ramy N. Tadros, Peter A. Beerel
Low Area, Low Power, Robust, Highly Sensitive Error Detecting Latch for Resilient Architectures. ISLPED (2016)
Ramy N. Tadros, Weizhe Hua, Matheus T. Moreira, Ney Laert Vilar Calazans, Peter A. Beerel
A Low-Power Low-Area Error-Detecting Latch for Resilient Architectures in 28-nm FDSOI. IEEE Trans. Circuits Syst. II Express Briefs (9) (2016)
Ramy N. Tadros, Weizhe Hua, Matheus Gibiluka, Matheus T. Moreira, Ney Laert Vilar Calazans, Peter A. Beerel
Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications. ASYNC (2016)