Ney Laert Vilar Calazans

Publication Activity (10 Years)

Years Active: 1994-2023
Publications (10 Years): 25

Top Topics

Software Development Environment

Delay Insensitive

Top Venues

Publications

Willian Analdo Nunes, Marcos Luiggi Lemos Sartori, Matheus Trevisan Moreira, Fernando Gehm Moraes, Ney Laert Vilar Calazans
Validating an Automated Asynchronous Synthesis Environment with a Challenging Design: RISC-V. SBCCI (2023)
Rodrigo N. Wuerdig, Marcos L. L. Sartori, Brunno A. Abreu, Sergio Bampi, Ney Laert Vilar Calazans
Mitigating Asynchronous QDI Drawbacks on MAC Operators with Approximate Multipliers. ISCAS (2022)
Marcos Luiggi Lemos Sartori, Willian Analdo Nunes, Ney Laert Vilar Calazans
Enhancing an Asynchronous Circuit Design Flow to Support Complex Digital System Design. SBCCI (2022)
Taciano A. Rodolfo, Marcos L. L. Sartori, Matheus T. Moreira, Ney Laert Vilar Calazans
Quasi Delay Insensitive FIFOs: Design Choices Exploration and Comparison. ISCAS (2021)
Marcos L. L. Sartori, Rodrigo N. Wuerdig, Matheus T. Moreira, Sergio Bampi, Ney Laert Vilar Calazans
Leveraging QDI Robustness to Simplify the Design of IoT Circuits. ISCAS (2020)
Paulo H. Vancin, Anderson R. P. Domingues, Marcelo Paravisi, Sergio F. Johann, Ney Laert Vilar Calazans, Alexandre M. Amory
Towards an Integrated Software Development Environment for Robotic Applications in MPSoCs with Support for Energy Estimations. ISCAS (2020)
Marcos L. L. Sartori, Matheus T. Moreira, Ney Laert Vilar Calazans
A Frontend using Traditional EDA Tools for the Pulsar QDI Design Flow. ASYNC (2020)
Rodrigo N. Wuerdig, Marcos L. L. Sartori, Ney Laert Vilar Calazans
Asynchronous Quasi-Random Number Generator: Taking Advantage of PVT Variations. LASCAS (2019)
Luiz Carlos Moreira, José Fontebasso Neto, Walter Silva Oliveira, Thiago Ferauche, Guilherme Heck, Ney Laert Vilar Calazans, Fernando Gehm Moraes
An IR-UWB pulse generator using PAM modulation with adaptive PSD in 130nm CMOS process. SBCCI (2019)
Marcos L. L. Sartori, Rodrigo N. Wuerdig, Matheus T. Moreira, Ney Laert Vilar Calazans
Pulsar: Constraining QDI Circuits Cycle Time Using Traditional EDA Tools. ASYNC (2019)
Matheus T. Moreira, Peter A. Beerel, Marcos L. L. Sartori, Ney Laert Vilar Calazans
NCL Synthesis With Conventional EDA Tools: Technology Mapping and Optimization. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2018)
Leandro S. Heck, Matheus T. Moreira, Ney Laert Vilar Calazans
Hardening C-elements against metastability. ICECS (2017)
Marcos L. L. Sartori, Ney Laert Vilar Calazans
Go functional model for a RISC-V asynchronous organisation - ARV. ICECS (2017)
Ricardo A. Guazzelli, Matheus T. Moreira, Ney Laert Vilar Calazans
A comparison of asynchronous QDI templates using static logic. LASCAS (2017)
Ricardo A. Guazzelli, Matheus T. Moreira, Walter Lau Neto, Ney Laert Vilar Calazans
Sleep convention logic isochronic fork: an analysis. SBCCI (2017)
Leonardo Rezende Juracy, Felipe B. Lazzarotto, Daniel V. Pigatto, Ney Laert Vilar Calazans, Fernando Gehm Moraes
XGT4: An industrial grade, open source tester for multi-gigabit networks. ICECS (2017)
Sergio Johann Filho, Matheus T. Moreira, Leandro S. Heck, Ney Laert Vilar Calazans, Fabiano Passuelo Hessel
A processor for IoT applications: An assessment of design space and trade-offs. Microprocess. Microsystems 42 (2016)
Ramy N. Tadros, Weizhe Hua, Matheus T. Moreira, Ney Laert Vilar Calazans, Peter A. Beerel
A Low-Power Low-Area Error-Detecting Latch for Resilient Architectures in 28-nm FDSOI. IEEE Trans. Circuits Syst. II Express Briefs (9) (2016)
Ajay Singhvi, Matheus T. Moreira, Ramy N. Tadros, Ney Laert Vilar Calazans, Peter A. Beerel
A Fine-Grain, Uniform, Energy-Efficient Delay Element for 2-Phase Bundled-Data Circuits. ACM J. Emerg. Technol. Comput. Syst. 13 (2) (2016)
Carlos Henrique Menezes Oliveira, Matheus T. Moreira, Ricardo A. Guazzelli, Ney Laert Vilar Calazans
ASCEnD-FreePDK45: An open source standard cell library for asynchronous design. ICECS (2016)
Yang Zhang, Leandro S. Heck, Matheus T. Moreira, David Zar, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel
Testable MUTEX Design. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2016)
Matheus Gibiluka, Matheus Trevisan Moreira, Walter Lau Neto, Ney Laert Vilar Calazans
A standard cell characterization flow for non-standard voltage supplies. SBCCI (2016)
Ramy N. Tadros, Weizhe Hua, Matheus Gibiluka, Matheus T. Moreira, Ney Laert Vilar Calazans, Peter A. Beerel
Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications. ASYNC (2016)
Felipe Todeschini Bortolon, Sergio Johann Filho, Matheus Gibiluka, Sergio Bampi, Ney Laert Vilar Calazans, Fabiano Passuelo Hessel, Matheus Trevisan Moreira
Design and analysis of the HF-RISC processor targeting voltage scaling applications. SBCCI (2016)
Sergio Johann Filho, Matheus T. Moreira, Ney Laert Vilar Calazans, Fabiano Passuelo Hessel
The HF-RISC processor: Performance assessment. LASCAS (2016)
Ajay Singhvi, Matheus T. Moreira, Ramy N. Tadros, Ney Laert Vilar Calazans, Peter A. Beerel
A Fine-Grained, Uniform, Energy-Efficient Delay Element for FD-SOI Technologies. ISVLSI (2015)
Guilherme Heck, Leandro S. Heck, Matheus T. Moreira, Fernando Gehm Moraes, Ney Laert Vilar Calazans
A digitally controlled oscillator for fine-grained local clock generators in MPSoCs. LASCAS (2015)
Peter A. Beerel, Ney Laert Vilar Calazans
A path towards average-case silicon via asynchronous resilient bundled-data design. ECCTD (2015)
Dylan Hand, Hsin-Ho Huang, Benmao Cheng, Yang Zhang, Matheus Trevisan Moreira, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel
Performance Optimization and Analysis of Blade Designs under Delay Variability. ASYNC (2015)
Guilherme Heck, Leandro S. Heck, Ajay Singhvi, Matheus T. Moreira, Peter A. Beerel, Ney Laert Vilar Calazans
Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits. VLSI Design (2015)
Ricardo A. Guazzelli, Fernando Gehm Moraes, Ney Laert Vilar Calazans, Matheus T. Moreira
SDDS-NCL Design: Analysis of Supply Voltage Scaling. SBCCI (2015)
Matheus Trevisan Moreira, Michel Evandro Arendt, Fernando Gehm Moraes, Ney Laert Vilar Calazans
Static Differential NCL Gates: Toward Low Power. IEEE Trans. Circuits Syst. II Express Briefs (6) (2015)
Yang Zhang, Leandro S. Heck, Matheus T. Moreira, David Zar, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel
Design and Analysis of Testable Mutual Exclusion Elements. ASYNC (2015)
Matheus Gibiluka, Matheus Trevisan Moreira, Ney Laert Vilar Calazans
A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA Framework. DSD (2015)
Matheus T. Moreira, Dylan Hand, Peter A. Beerel, Ney Laert Vilar Calazans
TDTB error detecting latches: Timing violation sensitivity analysis and optimization. ISQED (2015)
Dylan Hand, Matheus Trevisan Moreira, Hsin-Ho Huang, Danlei Chen, Frederico Butzke, Zhichao Li, Matheus Gibiluka, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel
Blade - A Timing Violation Resilient Asynchronous Template. ASYNC (2015)
Matheus Gibiluka, Matheus Trevisan Moreira, Fernando Gehm Moraes, Ney Laert Vilar Calazans
BAT-Hermes: A transition-signaling bundled-data NoC router. LASCAS (2015)
Matheus Trevisan Moreira, Michel Evandro Arendt, Ricardo Aquino Guazzelli, Ney Laert Vilar Calazans
A New CMOS Topology for Low-Voltage Null Convention Logic Gates Design. ASYNC (2014)
Matheus T. Moreira, Ney Laert Vilar Calazans
Advances on the state of the art in QDI design. VLSI-SoC (2014)
Matheus Trevisan Moreira, Fernando Gehm Moraes, Ney Laert Vilar Calazans
Beware the Dynamic C-Element. IEEE Trans. Very Large Scale Integr. Syst. 22 (7) (2014)
Adriel Ziesemer, Ricardo Reis, Matheus T. Moreira, Michel Evandro Arendt, Ney Laert Vilar Calazans
Automatic layout synthesis with ASTRAN applied to asynchronous cells. LASCAS (2014)
Everton Alceu Carara, Ney Laert Vilar Calazans, Fernando Gehm Moraes
Differentiated Communication Services for NoC-Based MPSoCs. IEEE Trans. Computers 63 (3) (2014)
Edson I. Moreno, Thais Webber, César A. M. Marcon, Fernando Gehm Moraes, Ney Laert Vilar Calazans
MoNoC: A monitored network on chip with path adaptation mechanism. J. Syst. Archit. 60 (10) (2014)
Matheus Trevisan Moreira, Ricardo Aquino Guazzelli, Guilherme Heck, Ney Laert Vilar Calazans
Hardening QDI circuits against transient faults using delay-insensitive maxterm synthesis. ACM Great Lakes Symposium on VLSI (2014)
Matheus Trevisan, Michel Evandro Arendt, Adriel Ziesemer, Ricardo Augusto da Luz Reis, Ney Laert Vilar Calazans
Automated Synthesis of Cell Libraries for Asynchronous Circuits. SBCCI (2014)
Taciano Perez, Ney Laert Vilar Calazans, César A. F. De Rose
System-level impacts of persistent main memory using a search engine. Microelectron. J. 45 (2) (2014)
Adriel Ziesemer, Ricardo Reis, Matheus T. Moreira, Michel Evandro Arendt, Ney Laert Vilar Calazans
A design flow for physical synthesis of digital cells with ASTRAN. ACM Great Lakes Symposium on VLSI (2014)
Matheus Trevisan Moreira, Guilherme Trojan, Fernando Gehm Moraes, Ney Laert Vilar Calazans
Spatially Distributed Dual-Spacer Null Convention Logic Design. J. Low Power Electron. 10 (3) (2014)
Matheus T. Moreira, Julian J. H. Pontes, Ney Laert Vilar Calazans
Tradeoffs between RTO and RTZ in WCHB QDI asynchronous design. ISQED (2014)
Ricardo A. Guazzelli, Guilherme Heck, Matheus T. Moreira, Ney Laert Vilar Calazans
Schmitt trigger on output inverters of NCL gates for soft error hardening: Is it enough? LATW (2014)
Matheus T. Moreira, Felipe G. Magalhaes, Matheus Gibiluka, Fabiano Hessel, Ney Laert Vilar Calazans
BaBaNoC: An asynchronous network-on-chip described in Balsa. RSP (2013)
Matheus Trevisan Moreira, Ney Laert Vilar Calazans
Design of standard-cell libraries for asynchronous circuits with the ASCEnD flow. ISVLSI (2013)
Alexandre M. Amory, Matheus T. Moreira, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Cristiano Lazzari, Marcelo Soares Lubaszewski
Evaluating the scalability of test buses. ISSoC (2013)
Matheus Trevisan Moreira, Carlos Henrique Menezes Oliveira, Ney Laert Vilar Calazans, Luciano Copello Ost
LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell Libraries. DSD (2013)
Matheus Trevisan Moreira, Ney Laert Vilar Calazans
Voltage scaling on C-elements: A speed, power and energy efficiency analysis. ICCD (2013)
Matheus T. Moreira, Carlos Henrique Menezes Oliveira, Ricardo C. Porto, Ney Laert Vilar Calazans
NCL+: Return-to-one Null Convention Logic. MWSCAS (2013)
Matheus T. Moreira, Bruno S. Oliveira, Fernando Gehm Moraes, Ney Laert Vilar Calazans
Charge sharing aware NCL gates design. DFTS (2013)
Matheus T. Moreira, Carlos Henrique Menezes Oliveira, Ricardo C. Porto, Ney Laert Vilar Calazans
Design of NCL gates with the ASCEnD flow. LASCAS (2013)
Bruno F. Ferreira, Ney Laert Vilar Calazans
A flexible soft IP core for standard implementations of elliptic curve cryptography in hardware. ICECS (2013)
Matheus T. Moreira, Ney Laert Vilar Calazans
Electrical characterization of a C-Element with LiChEn. ICECS (2012)
Matheus T. Moreira, Ricardo A. Guazzelli, Ney Laert Vilar Calazans
Return-to-One DIMS logic on 4-phase m-of-n asynchronous circuits. ICECS (2012)
Carlos A. Petry, Eduardo Wächter, Guilherme M. Castilhos, Fernando Gehm Moraes, Ney Laert Vilar Calazans
A spectrum of MPSoC models for design space exploration and its use. RSP (2012)
Fernando Gehm Moraes, Matheus T. Moreira, Carlos Lucas, D. Correa, Douglas de O. Cardoso, M. Magnaguagno, Guilherme M. Castilhos, Ney Laert Vilar Calazans
A generic FPGA emulation framework. ICECS (2012)
Matheus T. Moreira, Ricardo A. Guazzelli, Ney Laert Vilar Calazans
Return-to-one protocol for reducing static power in C-elements of QDI circuits employing m-of-n codes. SBCCI (2012)
Taciano Perez, Ney Laert Vilar Calazans, César A. F. De Rose
A preliminary study on system-level impact of persistent main memory. ISQED (2012)
Rafael Iankowski Soares, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Philippe Maurine, Lionel Torres
A Robust Architectural Approach for Cryptographic Algorithms Using GALS Pipelines. IEEE Des. Test Comput. 28 (5) (2011)
Edson I. Moreno, César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes
Arbitration and routing impact on NoC design. International Symposium on Rapid System Prototyping (2011)
Thiago R. da Rosa, Guilherme Montez Guindani, Douglas de O. Cardoso, Ney Laert Vilar Calazans, Fernando Gehm Moraes
A self-adaptable distributed DFS scheme for NoC-based MPSoCs. SBCCI (2011)
Juliano Benfica, Letícia Maria Bolzani Poehls, Fabian Vargas, José Lipovetzky, Ariel Lutenberg, Sebastián E. García, Edmundo Gatti, Fernando Hernandez, Ney Laert Vilar Calazans
Configurable platform for IC combined tests of total-ionizing dose radiation and electromagnetic immunity. LATW (2011)
Ewerson Luiz de Souza Carvalho, Ney Laert Vilar Calazans, Fernando Gehm Moraes
Dynamic Task Mapping for MPSoCs. IEEE Des. Test Comput. 27 (5) (2010)
Rafael Soares, Ney Laert Vilar Calazans, Victor Lomné, Amine Dehbaoui, Philippe Maurine, Lionel Torres
A GALS pipeline DES architecture to increase robustness against DPA and DEMA attacks. SBCCI (2010)
Guilherme Montez Guindani, Frederico Ferlini, Jeferson Oliveira, Ney Laert Vilar Calazans, Daniel V. Pigatto, Fernando Gehm Moraes
A 10 Gbps OTN Framer Implementation Targeting FPGA Devices. ReConFig (2009)
Taciano A. Rodolfo, Ney Laert Vilar Calazans, Fernando Gehm Moraes
Floating Point Hardware for Embedded Processors in FPGAs: Design Space Exploration for Performance and Area. ReConFig (2009)
Everton Carara, Roberto P. de Oliveira, Ney Laert Vilar Calazans, Fernando Gehm Moraes
HeMPS - a Framework for NoC-based MPSoC Generation. ISCAS (2009)
Edson Ifarraguirre Moreno, Katalin Maria Popovici, Ney Laert Vilar Calazans, Ahmed Amine Jerraya
Integrating Abstract NoC Models within MPSoC Design. IEEE International Workshop on Rapid System Prototyping (2008)
Julian J. H. Pontes, Matheus T. Moreira, Rafael Soares, Ney Laert Vilar Calazans
Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques. ISVLSI (2008)
Fernando Gehm Moraes, Everton Carara, Daniel V. Pigatto, Ney Laert Vilar Calazans
MOTIM: an industrial application using nocs. SBCCI (2008)
Rafael Soares, Ney Laert Vilar Calazans, Victor Lomné, Philippe Maurine, Lionel Torres, Michel Robert
Evaluating the robustness of secure triple track logic through prototyping. SBCCI (2008)
César Augusto Missio Marcon, Edson Ifarraguirre Moreno, Ney Laert Vilar Calazans, Fernando Gehm Moraes
Comparison of network-on-chip mapping algorithms targeting low energy consumption. IET Comput. Digit. Tech. 2 (6) (2008)
Ewerson Carvalho, Ney Laert Vilar Calazans, Fernando Gehm Moraes
Congestion-Aware Task Mapping in NoC-based MPSoCs with Dynamic Workload. ISVLSI (2007)
César A. M. Marcon, Edson I. Moreno, Ney Laert Vilar Calazans, Fernando Gehm Moraes
Evaluation of Algorithms for Low Energy Mapping onto NoCs. ISCAS (2007)
Erico Bastos, Everton Carara, Daniel V. Pigatto, Ney Laert Vilar Calazans, Fernando Moraes
MOTIM - A Scalable Architecture for Ethernet Switches. ISVLSI (2007)
Aline Mello, Ney Laert Vilar Calazans
Rate-based scheduling policy for QoS flows in networks on chip. VLSI-SoC (2007)
César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Igor M. Reis, Fabiano Hessel
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique CoRR (2007)
José Carlos S. Palma, César A. M. Marcon, Fernando Gehm Moraes, Ney Laert Vilar Calazans, Ricardo A. L. Reis, Altamiro Amadeu Susin
Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation. SBCCI (2005)
César A. M. Marcon, Márcio Eduardo Kreutz, Altamiro Amadeu Susin, Ney Laert Vilar Calazans
Models for Embedded Application Mapping onto NoCs: Timing Analysis. IEEE International Workshop on Rapid System Prototyping (2005)
Márcio Eduardo Kreutz, César A. M. Marcon, Luigi Carro, Altamiro Amadeu Susin, Ney Laert Vilar Calazans
Energy and latency evaluation of NoC topologies. ISCAS (6) (2005)
César A. M. Marcon, José Carlos S. Palma, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Ricardo Augusto da Luz Reis
Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs. VLSI-SoC (2005)
César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Igor M. Reis, Fabiano Hessel
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique. DATE (2005)
Leandro Möller, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Eduardo Wenzel Brião, Ewerson Carvalho, Daniel Camozzato
FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications. FPL (2004)
Ney Laert Vilar Calazans, Edson I. Moreno, Fabiano Hessel, Vitor M. da Rosa, Fernando Moraes, Everton Carara
From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study. SBCCI (2003)
Fernando Gehm Moraes, Daniel Mesquita, José Carlos S. Palma, Leandro Möller, Ney Laert Vilar Calazans
Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs. DATE (2003)
Fernando Gehm Moraes, Aline Mello, Leandro Möller, Luciano Ost, Ney Laert Vilar Calazans
A Low Area Overhead Packet-switched Network on Chip: Architecture and Prototyping. VLSI-SOC (2003)
Daniel Mesquita, Fernando Gehm Moraes, José Palma, Leandro Möller, Ney Laert Vilar Calazans
Remote and Partial Reconfiguration of FPGAs: Tools and Trends. IPDPS (2003)
César A. M. Marcon, Fabiano Hessel, Alexandre M. Amory, Luis H. L. Ries, Fernando Gehm Moraes, Ney Laert Vilar Calazans
Prototyping of embedded digital systems from SDL language: a case study. HLDVT (2002)
César Augusto Missio Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes
Requirements, Primitives and Models for Systems Specification. SBCCI (2002)
Ney Laert Vilar Calazans, Fernando Gehm Moraes
Integrating the teaching of computer organization and architecture with digital hardware design early in undergraduate courses. IEEE Trans. Educ. 44 (2) (2001)
Ney Laert Vilar Calazans, Fernando Gehm Moraes, Delfim Luiz Torok, Andrey V. Andreoli
Projeto para Prototipação de um IP Soft Core MAC Ethernet. RITA 8 (1) (2001)
Ney Laert Vilar Calazans
Boolean constrained encoding: a new formulation and a case study. ICCAD (1994)