Julian J. H. Pontes

ORCID

Publication Activity (10 Years)

Years Active: 2007-2021
Publications (10 Years): 2

Top Venues

Pontifícia Universidade Católica do Rio Grande do Sul, Porto Alegre, Brazil (PHD)

Education History

Pontifícia Universidade Católica do Rio Grande do Sul, Porto Alegre, Brazil

PHD

Publications

Pascal Vivet, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, César Fuguet Tortolero, Ivan Miro-Panades, Guillaume Moritz, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy
IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management. IEEE J. Solid State Circuits 56 (1) (2021)
Pascal Vivet, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, Guillaume Moritz, Ivan Miro-Panades, César Fuguet Tortolero, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy
@ 82%-Peak-Efficiency DC-DC Converters. ISSCC (2020)
Julian J. H. Pontes, Pascal Vivet, Yvain Thonnart
Two-phase protocol converters for 3D asynchronous 1-of-n data links. ASP-DAC (2015)
Matheus T. Moreira, Julian J. H. Pontes, Ney Laert Vilar Calazans
Tradeoffs between RTO and RTZ in WCHB QDI asynchronous design. ISQED (2014)
Julian J. H. Pontes, Ney Calazans, Pascal Vivet
Parity check for m-of-n delay insensitive codes. IOLTS (2013)
Julian J. H. Pontes, Ney Calazans, Pascal Vivet
H2A: A hardened asynchronous network on chip. SBCCI (2013)
Julian J. H. Pontes, Ney Calazans, Pascal Vivet
Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event Effects. ASYNC (2012)
Julian J. H. Pontes, Ney Calazans, Pascal Vivet
An accurate Single Event Effect digital design flow for reliable system level design. DATE (2012)
Matheus T. Moreira, Bruno Cruz de Oliveira, Julian J. H. Pontes, Fernando Moraes, Ney Calazans
Adapting a C-element design flow for low power. ICECS (2011)
Matheus T. Moreira, Bruno Cruz de Oliveira, Julian J. H. Pontes, Ney Calazans
A 65nm standard cell set and flow dedicated to automated asynchronous circuits design. SoCC (2011)
Julian J. H. Pontes, Matheus T. Moreira, Fernando Moraes, Ney Calazans
Hermes-AA: A 65nm asynchronous NoC router with adaptive routing. SoCC (2010)
Julian J. H. Pontes, Matheus T. Moreira, Fernando Moraes, Ney Calazans
Hermes-A - An Asynchronous NoC Router with Distributed Routing. PATMOS (2010)
Julian J. H. Pontes, Matheus T. Moreira, Rafael Soares, Ney Laert Vilar Calazans
Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques. ISVLSI (2008)
Julian J. H. Pontes, Rafael Soares, Ewerson Carvalho, Fernando Moraes, Ney Calazans
SCAFFI: An intrachip FPGA asynchronous interface based on hard macros. ICCD (2007)

Julian J. H. Pontes.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Julian J. H. Pontes