Adapting a C-element design flow for low power.

Matheus T. Moreira Bruno Cruz de Oliveira Julian J. H. Pontes Fernando Moraes Ney Calazans

Published in: ICECS (2011)

Keyphrases

low power
single chip
low cost
power consumption
vlsi architecture
high speed
low power consumption
logic circuits
gate array
digital signal processing
power dissipation
high power
ultra low power
wireless transmission
power reduction
cmos technology
design methodology