Edson I. Moreno

Publication Activity (10 Years)

Years Active: 2003-2014
Publications (10 Years): 0

Top Topics

Adaptation Strategies

Network On Chip

Top Venues

J. Syst. Archit.

Publications

Edson I. Moreno, Thais Webber, César A. M. Marcon, Fernando Gehm Moraes, Ney Laert Vilar Calazans
MoNoC: A monitored network on chip with path adaptation mechanism. J. Syst. Archit. 60 (10) (2014)
Edson I. Moreno, Thais Webber, César A. M. Marcon, Fernando Moraes, Ney Calazans
A monitored NoC with runtime path adaptation. ISCAS (2014)
Alexandre M. Amory, Edson I. Moreno, Fernando Moraes, Marcelo Lubaszewski
Determining the test sources/sinks for NoC TAMs. ISVLSI (2013)
Yan Ghidini, Thais Webber, Edson I. Moreno, Ivan Quadros, Rubem Dutra Ribeiro Fagundes, César A. M. Marcon
Topological impact on latency and throughput: 2D versus 3D NoC comparison. SBCCI (2012)
Yan Ghidini, Thais Webber, Edson I. Moreno, Fernando Grando, Rubem Dutra Ribeiro Fagundes, César A. M. Marcon
Buffer depth and traffic influence on 3D NoCs performance. RSP (2012)
Edson I. Moreno, César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes
Arbitration and routing impact on NoC design. International Symposium on Rapid System Prototyping (2011)
César A. M. Marcon, Ney Calazans, Edson I. Moreno, Fernando Moraes, Fabiano Hessel, Altamiro Amadeu Susin
CAFES: A framework for intrachip application modeling and communication architecture design. J. Parallel Distributed Comput. 71 (5) (2011)
César A. M. Marcon, Edson I. Moreno, Ney Laert Vilar Calazans, Fernando Gehm Moraes
Evaluation of Algorithms for Low Energy Mapping onto NoCs. ISCAS (2007)
Alexandre M. Amory, Marcelo Lubaszewski, Fernando Gehm Moraes, Edson I. Moreno
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture CoRR (2007)
Alexandre M. Amory, Marcelo Lubaszewski, Fernando Gehm Moraes, Edson I. Moreno
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture. DATE (2005)
Ney Laert Vilar Calazans, Edson I. Moreno, Fabiano Hessel, Vitor M. da Rosa, Fernando Moraes, Everton Carara
From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study. SBCCI (2003)