Login / Signup
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture
Alexandre M. Amory
Marcelo Lubaszewski
Fernando Gehm Moraes
Edson I. Moreno
Published in:
CoRR (2007)
Keyphrases
</>
network on chip
multi processor
single processor
packet switched
routing algorithm
parallel algorithm
parallel computers
real time
end to end
data flow