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Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture.
Alexandre M. Amory
Marcelo Lubaszewski
Fernando Gehm Moraes
Edson I. Moreno
Published in:
DATE (2005)
Keyphrases
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network on chip
multi processor
real time
parallel architecture
parallel algorithm
shared memory
distributed memory
single processor
high speed
parallel processing
routing algorithm
data flow
network simulator
packet switched