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A Low Area Overhead Packet-switched Network on Chip: Architecture and Prototyping.
Fernando Gehm Moraes
Aline Mello
Leandro Möller
Luciano Ost
Ney Laert Vilar Calazans
Published in:
VLSI-SOC (2003)
Keyphrases
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packet switched
network on chip
routing algorithm
multi processor
computer networks
network simulator
data transfer
interconnection networks
ad hoc networks
program execution
multipath
data streams
single processor
power dissipation
fault tolerant
routing protocol
signal processing
high speed