Login / Signup
Transistor Count Optimization in IG FinFET Network Design.
Vinicius N. Possani
André Inácio Reis
Renato P. Ribas
Felipe S. Marques
Leomar S. da Rosa Jr.
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2017)
Keyphrases
</>
network design
communication networks
facility location
network architecture
network design problem
heuristic solution
high speed
information gain
reverse logistics
neural network
decision trees
data analysis
optimization problems
ip networks
economic order quantity