CMOS logic gate performance variability related to transistor network arrangements.
Digeorgia N. da SilvaAndré Inácio ReisRenato P. RibasPublished in: Microelectron. Reliab. (2009)
Keyphrases
- high speed
- low power
- power consumption
- metal oxide semiconductor
- delay insensitive
- cmos technology
- computer networks
- low cost
- classical logic
- network structure
- network model
- peer to peer
- modal logic
- power supply
- real time
- community structure
- logic programming
- network architecture
- data flow
- circuit design
- silicon dioxide