Michael W. Beattie

Publication Activity (10 Years)

Years Active: 1997-2005
Publications (10 Years): 0

Publications

Michael W. Beattie, Hui Zheng, Anirudh Devgan, Byron Krauter
Spatially distributed 3D circuit models. DAC (2005)
Michael W. Beattie, Lawrence T. Pileggi
Parasitics extraction with multipole refinement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (2) (2004)
Hui Zheng, Lawrence T. Pileggi, Michael W. Beattie, Byron Krauter
Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses. DATE (2002)
Tao Lin, Michael W. Beattie, Lawrence T. Pileggi
On the efficacy of simplified 2D on-chip inductance models. DAC (2002)
Tao Lin, Michael W. Beattie, Lawrence T. Pileggi
On-Chip Inductance Models: 3D or Not 3D? DATE (2002)
Michael W. Beattie, Lawrence T. Pileggi
On-chip induction modeling: basics and advanced methods. IEEE Trans. Very Large Scale Integr. Syst. 10 (6) (2002)
Michael W. Beattie, Byron Krauter, Lale Alatan, Lawrence T. Pileggi
Equipotential shells for efficient inductance extraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (1) (2001)
Michael W. Beattie, Lawrence T. Pileggi
Modeling Magnetic Coupling for On-Chip Interconnect. DAC (2001)
Michael W. Beattie, Lawrence T. Pileggi
Efficient inductance extraction via windowing. DATE (2001)
Michael W. Beattie, Lawrence T. Pileggi
Inductance 101: Modeling and Extraction. DAC (2001)
Michael W. Beattie, Satrajit Gupta, Lawrence T. Pileggi
Hierarchical Interconnect Circuit Models. ICCAD (2000)
Michael W. Beattie, Lawrence T. Pileggi
Electromagnetic parasitic extraction via a multipole method with hierarchical refinement. ICCAD (1999)
Michael W. Beattie, Lawrence T. Pileggi
Error bounds for capacitance extraction via window techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (3) (1999)
Michael W. Beattie, Lawrence T. Pileggi
IC Analyses Including Extracted Inductance Models. DAC (1999)
Michael W. Beattie, Lawrence T. Pileggi
Bounds for BEM Capacitance Extraction. DAC (1997)