Ganesh Lakshminarayana

Publication Activity (10 Years)

Years Active: 1996-2006
Publications (10 Years): 0

Publications

Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana
The LOTTERYBUS on-chip communication architecture. IEEE Trans. Very Large Scale Integr. Syst. 14 (6) (2006)
Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
Input space-adaptive optimization for embedded-software synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (11) (2005)
Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
Memory binding for performance optimization of control-flow intensive behavioral descriptions. IEEE Trans. Very Large Scale Integr. Syst. 13 (5) (2005)
Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
Input space adaptive design: a high-level methodology for optimizing energy and performance. IEEE Trans. Very Large Scale Integr. Syst. 12 (6) (2004)
Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey
Common-case computation: a high-level energy and performance optimization technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (1) (2004)
Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey
Design of high-performance system-on-chips using communication architecture tuners. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (5) (2004)
Robert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
Analysis of power dissipation in embedded systems using real-time operating systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (5) (2003)
Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
Input Space Adaptive Embedded Software Synthesis. VLSI Design (2002)
Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ganesh Lakshminarayana
Optimizing public-key encryption for wireless clients. ICC (2002)
Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
High-level energy macromodeling of embedded software. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (9) (2002)
Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
High-level test compaction techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (7) (2002)
Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana
LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs. DAC (2001)
Nachiketh R. Potlapally, Michael S. Hsiao, Anand Raghunathan, Ganesh Lakshminarayana, Srimat T. Chakradhar
Accurate Power Macro-modeling Techniques for Complex RTL Circuits. VLSI Design (2001)
Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
TAO: regular expression-based register-transfer level testability analysis and optimization. IEEE Trans. Very Large Scale Integr. Syst. 9 (6) (2001)
Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
Testing of core-based systems-on-a-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (3) (2001)
Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
Input Space Adaptive Design: A High-level Methodology for Energy and Performance Optimization. DAC (2001)
Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
High-level Software Energy Macro-modeling. DAC (2001)
Vijay Raghunathan, Srivaths Ravi, Anand Raghunathan, Ganesh Lakshminarayana
Transient Power Management Through High Level Synthesis. ICCAD (2001)
Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis. IEEE Trans. Computers 49 (9) (2000)
Robert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
Power analysis of embedded operating systems. DAC (2000)
Vijay Raghunathan, Srivaths Ravi, Ganesh Lakshminarayana
High-Level Synthesis with Variable-Latency Components. VLSI Design (2000)
Vijay Raghunathan, Srivaths Ravi, Ganesh Lakshminarayana
Integrating variable-latency components into high-level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (10) (2000)
Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (8) (2000)
Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
Incorporating speculative execution into scheduling ofcontrol-flow-intensive designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (3) (2000)
Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
: Reducing test application time in high-level test generation. ITC (2000)
Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey
Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips. DAC (2000)
Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
High-level synthesis of low-power control-flow intensive circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (12) (1999)
Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST. VTS (1999)
Ganesh Lakshminarayana, Kamal S. Khouri, Niraj K. Jha
Wavesched: a novel scheduling technique for control-flow intensive designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (5) (1999)
Bharat P. Dave, Ganesh Lakshminarayana, Niraj K. Jha
COSYN: Hardware-software co-synthesis of heterogeneous distributed embedded systems. IEEE Trans. Very Large Scale Integr. Syst. 7 (1) (1999)
Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
A framework for testing core-based systems-on-a-chip. ICCAD (1999)
Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey
Power management in high-level synthesis. IEEE Trans. Very Large Scale Integr. Syst. 7 (1) (1999)
Ganesh Lakshminarayana, Niraj K. Jha
FACT: a framework for applying throughput and power optimizing transformations to control-flow-intensive behavioral descriptions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (11) (1999)
Ganesh Lakshminarayana, Niraj K. Jha
High-level synthesis of power-optimized and area-optimized circuits from hierarchical data-flow intensive behaviors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (3) (1999)
Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey
Common-Case Computation: A High-Level Technique for Power and Performance Optimization. DAC (1999)
Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
Memory binding for performance optimization of control-flow intensive behaviors. ICCAD (1999)
Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
Incorporating Speculative Execution into Scheduling of Control-Flow Intensive Behavioral Descriptions. DAC (1998)
Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
TAO: regular expression based high-level testability analysis and optimization. ITC (1998)
Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits. DATE (1998)
Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey
A Power Management Methodology for High-Level Synthesis. VLSI Design (1998)
Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
Fast high-level power estimation for control-flow intensive design. ISLPED (1998)
Ganesh Lakshminarayana, Niraj K. Jha
Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions. DAC (1998)
Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions. ICCAD (1998)
Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey
Transforming control-flow intensive designs to facilitate power management. ICCAD (1998)
Ganesh Lakshminarayana, Niraj K. Jha
: A Framework for the Application of Throughput and Power Optimizing Transformations to Control-Flow Intensive Behavioral Descriptions. DAC (1998)
Bharat P. Dave, Ganesh Lakshminarayana, Niraj K. Jha
COSYN: Hardware-Software Co-Synthesis of Embedded Systems. DAC (1997)
Ganesh Lakshminarayana, Kamal S. Khouri, Niraj K. Jha
Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptions. ICCAD (1997)
Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
Behavioral Synthesis of Fault Secure Controller?Datapaths using Aliasing Probability Analysis. FTCS (1996)