Santanu Mahapatra

Publication Activity (10 Years)

Years Active: 2002-2022
Publications (10 Years): 5

Top Topics

Monte Carlo Simulation

Field Effect Transistors

Top Venues

IET Circuits Devices Syst.

Publications

Arnab Kabiraj, Tripti Jain, Santanu Mahapatra
Massive Monte Carlo simulations-guided interpretable learning of two-dimensional Curie temperature. Patterns 3 (12) (2022)
Biswapriyo Das, Santanu Mahapatra
First Principles Based Compact Model for 2D-Channel MOSFETs. ISDCS (2020)
Madhuchhanda Brahma, Arnab Kabiraj, Santanu Mahapatra
Insights on Anisotropic Dissipative Quantum Transport in n-Type Phosphorene MOSFET. VLSI Design (2019)
Richa Chakravarty, Dipankar Saha, Santanu Mahapatra
New Asymmetric Atomistic Model for the Analysis of Phase-Engineered MoS2-Gold Top Contact. VLSI Design (2018)
Neha Sharan, Santanu Mahapatra
Compact noise modelling for common double-gate metal-oxide-semiconductor field-effect transistor adapted to gate-oxide-thickness asymmetry. IET Circuits Devices Syst. 10 (1) (2016)
Neha Sharan, Santanu Mahapatra
Small Signal Nonquasi-static Model for Common Double-Gate MOSFETs Adapted to Gate Oxide Thickness Asymmetry. VLSI Design (2014)
Surya Shankar Dan, Santanu Mahapatra
Impact of energy quantisation in single electron transistor island on hybrid complementary metal oxide semiconductor- single electron transistor integrated circuits. IET Circuits Devices Syst. 4 (5) (2010)
Sudipta Sarkar, Ananda S. Roy, Santanu Mahapatra
A Non Quasi-static Small Signal Model for Long Channel Symmetric DG MOSFET. VLSI Design (2010)
Surya Shankar Dan, Santanu Mahapatra
Analysis of the Energy Quantization Effects on Single Electron Inverter Performance through Noise Margin Modeling. VLSI Design (2009)
Ratul Kumar Baruah, Santanu Mahapatra
Concept of "Crossover Point" and its Application on Threshold Voltage Definition for Undoped-Body Transistors. VLSI Design (2009)
Biswajit Ray, Santanu Mahapatra
A New Threshold Voltage Model for Omega Gate Cylindrical Nanowire Transistor. VLSI Design (2008)
Nayan Patel, A. Ramesha, Santanu Mahapatra
Drive current boosting of n-type tunnel FET with strained SiGe layer at source. Microelectron. J. 39 (12) (2008)
Chaitanya Sathe, Santanu Mahapatra
Modeling and Analysis of Noise Margin in SET Logic. VLSI Design (2007)
Santanu Mahapatra, Kaustav Banerjee, Florent Pegeon, Adrian M. Ionescu
A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits. ICCAD (2003)
Adrian M. Ionescu, Michel J. Declercq, Santanu Mahapatra, Kaustav Banerjee, Jacques Gautier
Few electron devices: towards hybrid CMOS-SET integrated circuits. DAC (2002)
Santanu Mahapatra, Adrian M. Ionescu, Kaustav Banerjee, Michel J. Declercq
A SET quantizer circuit aiming at digital communication system. ISCAS (5) (2002)