Architecture and circuit design of parallel processing elements for de novo sequence assembly.
Yu-Long HuangChun-Shen LiuYu-Cheng LiYi-Chang LuPublished in: SoCC (2013)
Keyphrases
- processing elements
- circuit design
- massively parallel
- parallel computers
- hardware architecture
- image processing algorithms
- parallel architecture
- linear array
- parallel processors
- random access
- associative memory
- hardware implementation
- parallel architectures
- functional units
- single instruction multiple data
- multi core architecture
- distributed memory
- parallel computing
- parallel processing
- parallel algorithm
- image processing
- field programmable gate array
- data transfer
- multi core processors
- parallel implementation