Architecting On-Chip DRAM Cache for Simultaneous Miss Rate and Latency Reduction.
Fazal HameedLars BauerJörg HenkelPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2016)
Keyphrases
- highly efficient
- miss rate
- cache misses
- memory bandwidth
- main memory
- high density
- low cost
- memory subsystem
- replacement policy
- dynamic random access memory
- prefetching
- high speed
- data structure
- memory access
- buffer management
- low voltage
- database management systems
- low power
- single chip
- ibm power processor
- embedded dram