Abdelmajid Bouajila

Publication Activity (10 Years)

Years Active: 2006-2012
Publications (10 Years): 0

Top Topics

High Reliability

Parameter Optimization

Feature Extraction

Hyperparameters

Top Venues

Publications

Abdelmajid Bouajila, Abdallah Lakhtel, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf
A low-overhead monitoring ring interconnect for MPSoC parameter optimization. DDECS (2012)
Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf
An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft- and timing errors. DDECS (2011)
Johannes Zeppenfeld, Abdelmajid Bouajila, Andreas Herkersdorf, Walter Stechele
Towards Scalability and Reliability of Autonomic Systems on Chip. ISORC Workshops (2010)
Matthias May, Norbert Wehn, Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Daniel Ziener, Jürgen Teich
A rapid prototyping system for error-resilient multi-processor systems-on-chip. DATE (2010)
Johannes Zeppenfeld, Abdelmajid Bouajila, Walter Stechele, Andreas Herkersdorf
Learning Classifier Tables for Autonomic Systems on Chip. GI Jahrestagung (2) (2008)
Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel, Abdelmajid Bouajila, Walter Stechele, Andreas Herkersdorf
An Architecture for Runtime Evaluation of SoC Reliability. GI Jahrestagung (1) (2006)
Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel
Organic Computing at the System on Chip Level. VLSI-SoC (2006)
Abdelmajid Bouajila, Andreas Bernauer, Andreas Herkersdorf, Wolfgang Rosenstiel, Oliver Bringmann, Walter Stechele
Error Detection Techniques Applicable in an Architecture Framework and Design Methodology for Autonomic SoCs. BICC (2006)