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An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft- and timing errors.

Abdelmajid BouajilaJohannes ZeppenfeldWalter StecheleAndreas Herkersdorf
Published in: DDECS (2011)
Keyphrases
  • high speed
  • parallel architecture
  • single chip
  • low cost
  • digital signal
  • neural network
  • real time
  • information systems
  • signal processing
  • low power
  • parallel implementation
  • real time image processing