Andreas Becher

Publication Activity (10 Years)

Years Active: 2014-2024
Publications (10 Years): 31

Top Topics

Query Processing

Top Venues

ACM Trans. Reconfigurable Technol. Syst.

Publications

Jens Trautmann, Paul Krüger, Andreas Becher, Stefan Wildermann, Jürgen Teich
Design, Calibration, and Evaluation of Real-time Waveform Matching on an FPGA-based Digitizer at 10 GS/s. ACM Trans. Reconfigurable Technol. Syst. 17 (2) (2024)
Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Faramarz Khosravi, Andreas Becher, Jürgen Teich
Design and error analysis of accuracy-configurable sequential multipliers via segmented carry chains. it Inf. Technol. 64 (3) (2022)
Ali Asghar, Amanda Katherine Robillard, Ilya Tuzov, Andreas Becher, Daniel Ziener
Using Look Up Table Content as Signatures to Identify IP Cores in Modern FPGAs. ARCS (2022)
Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Stefan Wildermann, Jürgen Teich
Putting IMT to the Test: Revisiting and Expanding Interval Matching Techniques and their Calibration for SCA. ASHES@CCS (2022)
Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Jürgen Teich, Stefan Wildermann
Real-Time Waveform Matching with a Digitizer at 10 GS/s. CoRR (2022)
Franz-Josef Streit, Paul Krüger, Andreas Becher, Stefan Wildermann, Jürgen Teich
Design and Evaluation of a Tunable PUF Architecture for FPGAs. ACM Trans. Reconfigurable Technol. Syst. 15 (1) (2022)
Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Jürgen Teich, Stefan Wildermann
Real-Time Waveform Matching with a Digitizer at 10 GS/s. FPL (2022)
Tobias Hahn, Andreas Becher, Stefan Wildermann, Jürgen Teich
Raw Filtering of JSON Data on FPGAs. CoRR (2022)
Tobias Hahn, Andreas Becher, Stefan Wildermann, Jürgen Teich
Raw Filtering of JSON Data on FPGAs. DATE (2022)
Franz-Josef Streit, Paul Krüger, Andreas Becher, Jens Schlumberger, Stefan Wildermann, Jürgen Teich
Choice - A Tunable PUF-Design for FPGAs. FPL (2021)
Lekshmi Beena Gopalakrishnan Nair, Andreas Becher, Stefan Wildermann, Klaus Meyer-Wegener, Jürgen Teich
Speculative Dynamic Reconfiguration and Table Prefetching Using Query Look-Ahead in the ReProVide Near-Data-Processing System. Datenbank-Spektrum 21 (1) (2021)
Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Faramarz Khosravi, Andreas Becher, Jürgen Teich
On the Approximation of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains. CoRR (2021)
Franz-Josef Streit, Florian Fritz, Andreas Becher, Stefan Wildermann, Stefan Werner, Martin Schmidt-Korth, Michael Pschyklenk, Jürgen Teich
Secure Boot from Non-Volatile Memory for Programmable SoC Architectures. HOST (2020)
Lekshmi B. G., Andreas Becher, Klaus Meyer-Wegener
Query-Sequence Optimization on a Reconfigurable Hardware-Accelerated System. CoRR (2020)
Lekshmi B. G., Andreas Becher, Klaus Meyer-Wegener, Stefan Wildermann, Jürgen Teich
SQL Query Processing Using an Integrated FPGA-based Near-Data Accelerator in ReProVide. EDBT (2020)
Lekshmi Beena Gopalakrishnan Nair, Andreas Becher, Klaus Meyer-Wegener
The ReProVide query-sequence optimization in a hardware-accelerated DBMS. DaMoN (2020)
Franz-Josef Streit, Florian Fritz, Andreas Becher, Stefan Wildermann, Stefan Werner, Martin Schmidt-Korth, Michael Pschyklenk, Jürgen Teich
Secure Boot from Non-Volatile Memory for Programmable SoC Architectures. CoRR (2020)
Lekshmi B. G., Andreas Becher, Klaus Meyer-Wegener
The ReProVide Query-Sequence Optimization in a Hardware-Accelerated DBMS. CoRR (2020)
Patrick Plagwitz, Franz-Josef Streit, Andreas Becher, Stefan Wildermann, Jürgen Teich
Compiler-Based High-Level Synthesis of Application-Specific Processors on FPGAs. ReConFig (2019)
Andreas Becher, Achim Herrmann, Stefan Wildermann, Jürgen Teich
ReProVide: Towards Utilizing Heterogeneous Partially Reconfigurable Architectures for Near-Memory Data Processing. BTW (Workshops) (2019)
Andreas Becher, Jürgen Teich
In situ Statistics Generation within partially reconfigurable Hardware Accelerators for Query Processing. DaMoN (2019)
Franz-Josef Streit, Martín Letras, Stefan Wildermann, Benjamin Hackenberg, Joachim Falk, Andreas Becher, Jürgen Teich
Model-Based Design Automation of Hardware/Software Co-Designs for Xilinx Zynq PSoCs. ReConFig (2018)
Andreas Becher, Stefan Wildermann, Jürgen Teich
Optimistic regular expression matching on FPGAs for near-data processing. DaMoN (2018)
Andreas Becher, Lekshmi B. G., David Broneske, Tobias Drewes, Bala Gurumurthy, Klaus Meyer-Wegener, Thilo Pionteck, Gunter Saake, Jürgen Teich, Stefan Wildermann
Integration of FPGAs in Database Management Systems: Challenges and Opportunities. Datenbank-Spektrum 18 (3) (2018)
Jorge Echavarria, Katja Schutz, Andreas Becher, Stefan Wildermann, Jürgen Teich
Can Approximate Computing Reduce Power Consumption on FPGAs? ICECS (2018)
Jutta Pirkl, Andreas Becher, Jorge Echavarria, Jürgen Teich, Stefan Wildermann
Self-Adaptive FPGA-Based Image Processing Filters Using Approximate Arithmetics. SCOPES (2017)
Andreas Becher, Jorge Echavarria, Daniel Ziener, Stefan Wildermann, Jürgen Teich
A LUT-Based Approximate Adder. FCCM (2016)
Daniel Ziener, Florian Bauer, Andreas Becher, Christopher Dennl, Klaus Meyer-Wegener, Ute Schürfeld, Jürgen Teich, Jörg-Stephan Vogt, Helmut Weber
FPGA-Based Dynamically Reconfigurable SQL Query Processing. ACM Trans. Reconfigurable Technol. Syst. 9 (4) (2016)
Andreas Becher, Stefan Wildermann, Moritz Mühlenthaler, Jürgen Teich
ReOrder: Runtime datapath generation for high-throughput multi-stream processing. ReConFig (2016)
Jorge Echavarria, Stefan Wildermann, Andreas Becher, Jürgen Teich, Daniel Ziener
FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs. FPT (2016)
Andreas Becher, Jutta Pirkl, Achim Herrmann, Jürgen Teich, Stefan Wildermann
Hybrid energy-aware reconfiguration management on Xilinx Zynq SoCs. ReConFig (2016)
Andreas Becher, Daniel Ziener, Klaus Meyer-Wegener, Jürgen Teich
A co-design approach for accelerated SQL query processing via FPGA-based data filtering. FPT (2015)
Robért Glein, Florian Rittner, Andreas Becher, Daniel Ziener, Jürgen Frickel, Jürgen Teich, Albert Heuberger
Reliability of space-grade vs. COTS SRAM-based FPGA in N-modular redundancy. AHS (2015)
Andreas Becher, Florian Bauer, Daniel Ziener, Jürgen Teich
Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration. FPL (2014)