Thilo Pionteck

ORCID

Publication Activity (10 Years)

Years Active: 2000-2024
Publications (10 Years): 64

Top Venues

Publications

Max Tzschoppe, Daniele Passaretti, Amir Najafi, Sebastian Fischer, Martin Wilhelm, Alberto García-Ortiz, Thilo Pionteck
Impact of Wave Pipelining on NoCs for Heterogeneous Monolithic 3D SoCs. MOCAST (2024)
Gerald Krell, Thilo Pionteck
Large Filter Low-Level Processing by Edge TPU. VISIGRAPP (3): VISAPP (2024)
Daniele Passaretti, Thilo Pionteck
On-the-Fly CT Image Pre-processing on MPSoC-FPGAs. ARCS (2024)
Anna Drewes, Vitalii Burtsev, Bala Gurumurthy, Martin Wilhelm, David Broneske, Gunter Saake, Thilo Pionteck
An Architectural Template for FPGA Overlays Targeting Data Flow Applications. IPDPS (Workshops) (2024)
Tobias Groth, Sven Groppe, Thilo Pionteck, Franz Valdiek, Martin Koppehel
Hybrid CPU/GPU/APU accelerated query, insert, update and erase operations in hash tables with string keys. Knowl. Inf. Syst. 65 (10) (2023)
Bala Gurumurthy, Vasudev Raghavendra Bidarkar, David Broneske, Thilo Pionteck, Gunter Saake
What Happens When Two Multi-Query Optimization Paradigms Combine? - A Hybrid Shared Sub-Expression (SSE) and Materialized View Reuse (MVR) Study. ADBIS (2023)
Vitalii Burtsev, Martin Wilhelm, Anna Drewes, Bala Gurumurthy, David Broneske, Thilo Pionteck, Gunter Saake
FPGA-Integrated Bag of Little Bootstraps Accelerator for Approximate Database Query Processing. ARC (2023)
Daniele Passaretti, Thilo Pionteck
A Control Data Acquisition System Architecture for MPSoC-FPGAs in Computed Tomography. ARC (2023)
Bala Gurumurthy, David Broneske, Martin Schäler, Thilo Pionteck, Gunter Saake
Novel insights on atomic synchronization for sort-based group-by on GPUs. Distributed Parallel Databases 41 (3) (2023)
Anna Drewes, Vitalii Burtsev, Bala Gurumurthy, Martin Wilhelm, David Broneske, Gunter Saake, Thilo Pionteck
A Flexible and Scalable Reconfigurable FPGA Overlay Architecture for Data-Flow Processing. FCCM (2023)
Daniele Passaretti, Max Steiger, Thilo Pionteck
Enabling Plug-and-Play in Cyber-Physical Systems Using MPSoC-FPGAs. IEEE Access 11 (2023)
Martin Wilhelm, Hanna Geppert, Anna Drewes, Thilo Pionteck
A comprehensive modeling approach for the task mapping problem in heterogeneous systems with dataflow processing units. Concurr. Comput. Pract. Exp. 35 (25) (2023)
Bala Gurumurthy, David Broneske, Gabriel Campero Durand, Thilo Pionteck, Gunter Saake
ADAMANT: A Query Executor with Plug-In Interfaces for Easy Co-processor Integration. ICDE (2023)
Tobias Groth, Sven Groppe, Thilo Pionteck, Franz Valdiek, Martin Koppehel
Accelerated Parallel Hybrid GPU/CPU Hash Table Queries with String Keys. DEXA (2) (2022)
Jan Moritz Joseph, Lennart Bamberg, Imad Hajjar, Behnam Razi Perjikolaei, Alberto García-Ortiz, Thilo Pionteck
Ratatoskr: An Open-Source Framework for In-Depth Power, Performance, and Area Analysis and Optimization in 3D NoCs. ACM Trans. Model. Comput. Simul. 32 (1) (2022)
Martin Wilhelm, Hanna Geppert, Anna Drewes, Thilo Pionteck
Modeling Task Mapping for Data-intensive Applications in Heterogeneous Systems. CoRR (2022)
Daniele Passaretti, Felix Boehm, Martin Wilhelm, Thilo Pionteck
Hardware Isolation Support for Low-Cost SoC-FPGAs. ARCS (2022)
Martin Wilhelm, Hanna Geppert, Anna Drewes, Thilo Pionteck
Modeling Task Mapping for Data-Intensive Applications in Heterogeneous Systems. Euro-Par Workshops (2022)
Christopher Blochwitz, León Philipp, Mladen Berekovic, Thilo Pionteck
StreamGrid - An AXI-Stream-Compliant Overlay Architecture. ARC (2021)
Jan Moritz Joseph, Ananda Samajdar, Lingjun Zhu, Rainer Leupers, Sung Kyu Lim, Thilo Pionteck, Tushar Krishna
Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators. ISQED (2021)
Bala Gurumurthy, David Broneske, Martin Schäler, Thilo Pionteck, Gunter Saake
An Investigation of Atomic Synchronization for Sort-Based Group-By Aggregation on GPUs. ICDE Workshops (2021)
Anna Drewes, Martin Koppehel, Thilo Pionteck
Dead-Ends in FPGAs for Database Acceleration. SAMOS (2021)
Daniele Passaretti, Thilo Pionteck
Configurable Pipelined Datapath for Data Acquisition in Interventional Computed Tomography. FCCM (2021)
Jan Moritz Joseph, Lennart Bamberg, Geonhwa Jeong, Ruei-Ting Chien, Rainer Leupers, Alberto García-Ortiz, Tushar Krishna, Thilo Pionteck
Bridging the Frequency Gap in Heterogeneous 3D SoCs through Technology-Specific NoC Router Architectures. ASP-DAC (2021)
Martin Koppehel, Tobias Groth, Sven Groppe, Thilo Pionteck
CuART - a CUDA-based, scalable Radix-Tree lookup and update engine. ICPP (2021)
David Broneske, Anna Drewes, Bala Gurumurthy, Imad Hajjar, Thilo Pionteck, Gunter Saake
In-Depth Analysis of OLAP Query Performance on Heterogeneous Hardware. Datenbank-Spektrum 21 (2) (2021)
Anna Drewes, Jan Moritz Joseph, Bala Gurumurthy, David Broneske, Gunter Saake, Thilo Pionteck
Optimising Operator Sets for Analytical Database Processing on FPGAs. ARC (2020)
Jan Moritz Joseph, Ananda Samajdar, Lingjun Zhu, Rainer Leupers, Sung Kyu Lim, Thilo Pionteck, Tushar Krishna
Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators. CoRR (2020)
Daniele Passaretti, Thilo Pionteck
Hardware/Software Co-Design of a control and data acquisition system for Computed Tomography. MOCAST (2020)
Dennis Heinrich, Stefan Werner, Christopher Blochwitz, Thilo Pionteck, Sven Groppe
Hardware-aided update acceleration in a hybrid Semantic Web database system. J. Supercomput. 76 (10) (2020)
Balasubramanian Gurumurthy, Imad Hajjar, David Broneske, Thilo Pionteck, Gunter Saake
When Vectorwise Meets Hyper, Pipeline Breakers Become the Moderator. ADMS@VLDB (2020)
Tobias Groth, Sven Groppe, Martin Koppehel, Thilo Pionteck
Parallelizing Approximate Search on Adaptive Radix Trees. SEBD (2020)
Martin Koppehel, Thilo Pionteck
Ultra-Low-Latency Video Encoding on Heterogenous Hardware Platforms. FPT (2020)
Michael Müller, Thomas Leich, Thilo Pionteck, Gunter Saake, Jens Teubner, Olaf Spinczyk
He..ro DB: A Concept for Parallel Data Processing on Heterogeneous Hardware. ARCS (2020)
Jan Moritz Joseph, Dominik Ermel, Lennart Bamberg, Alberto García Ortiz, Thilo Pionteck
System-Level Optimization of Network-on-Chips for Heterogeneous 3D System-on-Chips. ICCD (2019)
Daniele Passaretti, Jan Moritz Joseph, Thilo Pionteck
Survey on FPGAs in Medical Radiology Applications: Challenges, Architectures and Programming Models. FPT (2019)
Jan Moritz Joseph, Lennart Bamberg, Dominik Ermel, Behnam Razi Perjikolaei, Anna Drewes, Alberto García-Ortiz, Thilo Pionteck
NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures. CoRR (2019)
Jan Moritz Joseph, Dominik Ermel, Tobias Drewes, Lennart Bamberg, Alberto García-Ortiz, Thilo Pionteck
Area Optimization with Non-Linear Models in Core Mapping for System-on-Chips. MOCAST (2019)
Jan Moritz Joseph, Lennart Bamberg, Imad Hajjar, Behnam Razi Perjikolaei, Alberto García Ortiz, Thilo Pionteck
Ratatoskr: An open-source framework for in-depth power, performance and area analysis in 3D NoCs. CoRR (2019)
Jan Moritz Joseph, Lennart Bamberg, Imad Hajjar, Robert Schmidt, Thilo Pionteck, Alberto García Ortiz
Simulation environment for link energy estimation in networks-on-chip with virtual channels. Integr. 68 (2019)
Jan Moritz Joseph, Lennart Bamberg, Dominik Ermel, Behnam Razi Perjikolaei, Anna Drewes, Alberto García Ortiz, Thilo Pionteck
NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures. IEEE Access 7 (2019)
Lennart Bamberg, Jan Moritz Joseph, Thilo Pionteck, Alberto García Ortiz
Crosstalk optimization for through-silicon vias by exploiting temporal signal misalignment. Integr. 67 (2019)
Jan Moritz Joseph, Dominik Ermel, Lennart Bamberg, Alberto García Ortiz, Thilo Pionteck
System-level optimization of Network-on-Chips for heterogeneous 3D System-on-Chips. CoRR (2019)
Jan Moritz Joseph, Lennart Bamberg, Gerald Krell, Imad Hajjar, Alberto García Ortiz, Thilo Pionteck
Specification of Simulation Models for NoCs in Heterogeneous 3D SoCs. ReCoSoC (2018)
Bala Gurumurthy, Tobias Drewes, David Broneske, Gunter Saake, Thilo Pionteck
Adaptive Data Processing in Heterogeneous Hardware Systems. Grundlagen von Datenbanken (2018)
Bala Gurumurthy, David Broneske, Tobias Drewes, Thilo Pionteck, Gunter Saake
Cooking DBMS Operations using Granular Primitives - An Overview on a Primitive-based RDBMS Query Evaluation. Datenbank-Spektrum 18 (3) (2018)
Andreas Becher, Lekshmi B. G., David Broneske, Tobias Drewes, Bala Gurumurthy, Klaus Meyer-Wegener, Thilo Pionteck, Gunter Saake, Jürgen Teich, Stefan Wildermann
Integration of FPGAs in Database Management Systems: Challenges and Opportunities. Datenbank-Spektrum 18 (3) (2018)
Christopher Blochwitz, Julian Wolff, Mladen Berekovic, Dennis Heinrich, Sven Groppe, Jan Moritz Joseph, Thilo Pionteck
Hardware-Accelerated Index Construction for Semantic Web. FPT (2018)
Lennart Bamberg, Jan Moritz Joseph, Robert Schmidt, Thilo Pionteck, Alberto García Ortiz
Coding-aware Link Energy Estimation for 2D and 3D Networks-on-Chip with Virtual Channels. PATMOS (2018)
Tobias Drewes, Jan Moritz Joseph, Bala Gurumurthy, David Broneske, Gunter Saake, Thilo Pionteck
Efficient Inter-Kernel Communication for OpenCL Database Operators on FPGAs. FPT (2018)
Christopher Blochwitz, Raphael Klink, Jan Moritz Joseph, Thilo Pionteck
Continuous live-tracing as debugging approach on FPGAs. ReConFig (2017)
Jan Moritz Joseph, Morten Mey, Kristian Ehlers, Christopher Blochwitz, Tobias Winker, Thilo Pionteck
Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS. ReConFig (2017)
Stefan Werner, Dennis Heinrich, Thilo Pionteck, Sven Groppe
Semi-static operator graphs for accelerated query execution on FPGAs. Microprocess. Microsystems 53 (2017)
Jan Moritz Joseph, Lennart Bamberg, Sven Wrieden, Dominik Ermel, Alberto García Ortiz, Thilo Pionteck
Design method for asymmetric 3D interconnect architectures with high level models. ReCoSoC (2017)
Christopher Blochwitz, Julian Wolff, Jan Moritz Joseph, Stefan Werner, Dennis Heinrich, Sven Groppe, Thilo Pionteck
Hardware-Accelerated Radix-Tree Based String Sorting for Big Data Applications. ARCS (2017)
Jan Moritz Joseph, Christopher Blochwitz, Alberto García Ortiz, Thilo Pionteck
Area and power savings via asymmetric organization of buffers in 3D-NoCs for heterogeneous 3D-SoCs. Microprocess. Microsystems 48 (2017)
Tobias Drewes, Jan Moritz Joseph, Thilo Pionteck
An FPGA-based prototyping framework for Networks-on-Chip. ReConFig (2017)
Jan Moritz Joseph, Tobias Winker, Kristian Ehlers, Christopher Blochwitz, Thilo Pionteck
Hardware-accelerated pose estimation for embedded systems using Vivado HLS. ReConFig (2016)
Stefan Werner, Dennis Heinrich, Sven Groppe, Christopher Blochwitz, Thilo Pionteck
Runtime Adaptive Hybrid Query Engine based on FPGAs. Open J. Databases 3 (1) (2016)
Michael Raitza, Markus Vogt, Christian Hochberger, Thilo Pionteck
RAW 2014: Random Number Generators on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 9 (2) (2016)
Jan Moritz Joseph, Sven Wrieden, Christopher Blochwitz, Alberto García Ortiz, Thilo Pionteck
A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip. ReCoSoC (2016)
Stefan Werner, Dennis Heinrich, Marc Stelzner, Volker Linnemann, Thilo Pionteck, Sven Groppe
Accelerated join evaluation in Semantic Web databases by using FPGAs. Concurr. Comput. Pract. Exp. 28 (7) (2016)
Jan Moritz Joseph, Christopher Blochwitz, Thilo Pionteck
Adaptive allocation of default router paths in Network-on-Chips for latency reduction. HPCS (2016)
Sven Groppe, Dennis Heinrich, Christopher Blochwitz, Thilo Pionteck
Constructing Large-Scale Semantic Web Indices for the Six RDF Collation Orders. Open J. Big Data 2 (1) (2016)
Sven Groppe, Dennis Heinrich, Stefan Werner, Christopher Blochwitz, Thilo Pionteck
PatTrieSort - External String Sorting based on Patricia Tries. Open J. Databases 2 (1) (2015)
Stefan Werner, Dennis Heinrich, Jannik Piper, Sven Groppe, Rico Backasch, Christopher Blochwitz, Thilo Pionteck
Automated composition and execution of hardware-accelerated operator graphs. ReCoSoC (2015)
Dennis Heinrich, Stefan Werner, Marc Stelzner, Christopher Blochwitz, Thilo Pionteck, Sven Groppe
tree in a Semantic Web database system. ReCoSoC (2015)
Jan Moritz Joseph, Christopher Blochwitz, Thilo Pionteck, Alberto García Ortiz
Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs. NORCAS (2015)
Christopher Blochwitz, Jan Moritz Joseph, Rico Backasch, Thilo Pionteck, Stefan Werner, Dennis Heinrich, Sven Groppe
An optimized radix-tree for hardware-accelerated dictionary generation for semantic web databases. ReConFig (2015)
Rico Backasch, Gerald Hempel, Christopher Blochwitz, Stefan Werner, Sven Groppe, Thilo Pionteck
An architectural template for composing application specific datapaths at runtime. ReConFig (2015)
Jan Moritz Joseph, Thilo Pionteck
A cycle-accurate Network-on-Chip simulator with support for abstract task graph modeling. ISSoC (2014)
Rico Backasch, Gerald Hempel, Stefan Werner, Sven Groppe, Thilo Pionteck
Identifying homogenous reconfigurable regions in heterogeneous FPGAs for module relocation. ReConFig (2014)
Michael Raitza, Markus Vogt, Christian Hochberger, Thilo Pionteck
Influence of Magnetic Fields and X-Radiation on Ring Oscillators in FPGAs. IPDPS Workshops (2014)
Stefan Werner, Dennis Heinrich, Marc Stelzner, Sven Groppe, Rico Backasch, Thilo Pionteck
Parallel and Pipelined Filter Operator for Hardware-Accelerated Operator Graphs in Semantic Web Databases. CIT (2014)
Thilo Pionteck, Christoph Osterloh
Prioritizing semi-static data streams in network-on-chips for runtime reconfigurable systems. HPCS (2013)
Gerald Hempel, Jan Hoyer, Thilo Pionteck, Christian Hochberger
Register allocation for high-level synthesis of hardware accelerators targeting FPGAs. ReCoSoC (2013)
Stefan Werner, Sven Groppe, Volker Linnemann, Thilo Pionteck
Hardware-accelerated join processing in large Semantic Web databases with FPGAs. HPCS (2013)
Christoph Osterloh, Thilo Pionteck, Erik Maehle
MONSUN II: A small and inexpensive AUV for underwater swarms. ROBOTIK (2012)
Volker Hampel, Thilo Pionteck, Erik Maehle
An Approach for Performance Estimation of Hybrid Systems with FPGAs and GPUs as Coprocessors. ARCS (2012)
Thilo Pionteck, Christoph Osterloh, Carsten Albrecht
Linking Formal Description and Simulation of Runtime Reconfigurable Systems. ReConFig (2011)
Thilo Pionteck, Werner Brockmann
A concept of a trust management architecture to increase the robustness of nano age devices. DSN Workshops (2010)
Thilo Pionteck, Steffen Sammann, Carsten Albrecht
Optimizing Runtime Reconfiguration Decisions. EUC (2010)
Thilo Pionteck, Roman Koch, Carsten Albrecht, Erik Maehle
A Design Technique for Adapting Number and Boundaries of Reconfigurable Modules at Runtime. Int. J. Reconfigurable Comput. 2009 (2009)
Carsten Albrecht, Roman Koch, Thilo Pionteck, Erik Maehle, Michael Werner, Rudolf Fuchsen
WCET determination tool for embedded systems software. SimuTools (2008)
Thilo Pionteck, Carsten Albrecht, Roman Koch, Erik Maehle
On the design parameters of runtime reconfigurable systems. FPL (2008)
Thilo Pionteck, Carsten Albrecht, Roman Koch, Erik Maehle
Adaptive Communication Architectures for Runtime Reconfigurable System-on-Chips. Parallel Process. Lett. 18 (2) (2008)
Thilo Pionteck, Carsten Albrecht, Roman Koch, Torben Brix, Erik Maehle
Design and Simulation of Runtime Reconfigurable Systems. DDECS (2008)
Thilo Pionteck, Roman Koch, Carsten Albrecht, Erik Maehle, Michael Meitinger, Rainer Ohlendorf, Thomas Wild, Andreas Herkersdorf
Network processors. FPL (2008)
Carsten Albrecht, Philipp Roß, Roman Koch, Thilo Pionteck, Erik Maehle
Performance Analysis of Bus-Based Interconnects for a Run-Time Reconfigurable Co-Processor Platform. PDP (2008)
Roman Koch, Thilo Pionteck, Carsten Albrecht, Erik Maehle
A Lightweight Framework for Runtime Reconfigurable System Prototyping. IEEE International Workshop on Rapid System Prototyping (2007)
Heiko Hinkelmann, Peter Zipf, Manfred Glesner, Thilo Pionteck
Dynamically Reconfigurable Computing for Wireless Communication Systems (Dynamisch rekonfigurierbares Rechnen für Mobilfunksysteme). it Inf. Technol. 49 (3) (2007)
Thilo Pionteck
Teaching Informatics Students the Secrets of Hardware Design. MSE (2007)
Thilo Pionteck, Carsten Albrecht, Roman Koch, Erik Maehle, Michael Hübner, Jürgen Becker
Communication Architectures for Dynamically Reconfigurable FPGA Designs. IPDPS (2007)
Thilo Pionteck, Roman Koch, Carsten Albrecht
Applying Partial Reconfiguration to Networks-On-Chips. FPL (2006)
Thilo Pionteck, Carsten Albrecht, Roman Koch
A dynamically reconfigurable packet-switched network-on-chip. DATE (2006)
Roman Koch, Thilo Pionteck, Carsten Albrecht, Erik Maehle
An adaptive system-on-chip for network applications. IPDPS (2006)
Peter Zipf, Volker Hampel, Manfred Glesner, Thilo Pionteck
Eine Scheduling Heuristik zur Minimierung der Verlustleistung. MBMV (2006)
Manfred Glesner, Heiko Hinkelmann, Thomas Hollstein, Leandro Soares Indrusiak, Tudor Murgan, Abdulfattah Mohammad Obeid, Mihail Petrov, Thilo Pionteck, Peter Zipf
Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques. SAMOS (2005)
Heiko Hinkelmann, Thilo Pionteck, Oliver Kleine, Manfred Glesner
Prozessorintegration und Speicheranbindung dynamisch rekonfigurierbarer Funktionseinheiten. ARCS Workshops (2005)
Thilo Pionteck, Thomas Stiefmeier, Thorsten Staake, Manfred Glesner
On The Design of A Dynamically Reconfigurable Function-Unit for Error Detection and Correction. VLSI-SoC (2005)

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Publication Activity (10 Years)

Top Topics

Top Venues

Thilo Pionteck