Register allocation for high-level synthesis of hardware accelerators targeting FPGAs.
Gerald HempelJan HoyerThilo PionteckChristian HochbergerPublished in: ReCoSoC (2013)
Keyphrases
- high level synthesis
- parallel architecture
- field programmable gate array
- hardware implementation
- resource allocation
- design space exploration
- optimal allocation
- computer vision
- pattern recognition
- hardware software
- signal processing
- parallel processing
- embedded systems
- combinatorial auctions
- distributed systems
- allocation scheme
- multi agent