Performance Analysis of Bus-Based Interconnects for a Run-Time Reconfigurable Co-Processor Platform.
Carsten AlbrechtPhilipp RoßRoman KochThilo PionteckErik MaehlePublished in: PDP (2008)
Keyphrases
- high speed
- systolic array
- digital signal
- parallel architecture
- reconfigurable architecture
- input output
- fiber optic
- low cost
- central processor
- distributed memory
- hardware implementation
- lower cost
- fine grain
- instruction set
- reconfigurable hardware
- compute intensive
- parallel processing
- real time
- single chip
- mobile applications
- parallel algorithm
- computer systems