Christopher T. Clarke

Publication Activity (10 Years)

Years Active: 1998-2020
Publications (10 Years): 3

Top Topics

Field Programmable Gate Array

Hardware Architecture

Hardware Implementation

Signal Processing

Top Venues

ACM Trans. Reconfigurable Technol. Syst.

ACM Trans. Embed. Comput. Syst.

Publications

Alexander E. Beasley, Christopher T. Clarke, Robert J. Watson
An OpenGL Compliant Hardware Implementation of a Graphic Processing Unit Using Field Programmable Gate Array-System on Chip Technology. ACM Trans. Reconfigurable Technol. Syst. 14 (1) (2020)
Alexander E. Beasley, Robert J. Watson, Christopher T. Clarke
Efficient digital implementation of a multi-precision square-root algorithm. IET Comput. Digit. Tech. 13 (2) (2019)
Alok Prakash, Christopher T. Clarke, Siew-Kei Lam, Thambipillai Srikanthan
Rapid Memory-Aware Selection of Hardware Accelerators in Programmable SoC Design. IEEE Trans. Very Large Scale Integr. Syst. 26 (3) (2018)
Siew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke
Rapid evaluation of custom instruction selection approaches with FPGA estimation. ACM Trans. Embed. Comput. Syst. 13 (4) (2014)
Siew Kei Lam, Christopher T. Clarke, Thambipillai Srikanthan
Exploiting FPGA-Aware Merging of Custom Instructions for Runtime Reconfiguration. ACM Trans. Reconfigurable Technol. Syst. 7 (3) (2014)
Assad I. Al-Shueli, Christopher T. Clarke, Nick Donaldson, John Taylor
Improved Signal Processing Methods for Velocity Selective Neural Recording Using Multi-Electrode Cuffs. IEEE Trans. Biomed. Circuits Syst. 8 (3) (2014)
Alok Prakash, Siew Kei Lam, Christopher T. Clarke, Thambipillai Srikanthan
FPGA-aware techniques for rapid generation of profitable custom instructions. Microprocess. Microsystems 37 (3) (2013)
Alok Prakash, Siew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke
Modelling communication overhead for accessing local memories in hardware accelerators. ASAP (2013)
Di Wang, Christopher T. Clarke, A. N. Evans
Examination of the concept of a row-column separated median filter. FPL (2012)
Siew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke
Exploiting FPGA-aware merging of custom instructions for runtime reconfiguration. ReCoSoC (2012)
Alok Prakash, Christopher T. Clarke, Thambipillai Srikanthan
Custom instructions with local memory elements without expensive DMA transfers. FPL (2012)
Siew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke
Architecture-Aware Technique for Mapping Area-Time Efficient Custom Instructions onto FPGAs. IEEE Trans. Computers 60 (5) (2011)
Alok Prakash, Siew Kei Lam, Christopher T. Clarke, Thambipillai Srikanthan
Instruction set customization for area-constrained FPGA designs. SoCC (2011)
Siew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke
Selecting Profitable Custom Instructions for Area-Time-Efficient Realization on Reconfigurable Architectures. IEEE Trans. Ind. Electron. 56 (10) (2009)
Christopher T. Clarke, John Taylor, Xianhong Xu
Analogue/digital interface and communications aspects in a multi-channel ENG recording asic. ISCAS (2008)
Suchitra Sathyanarayana, Srikanthan Thambipillai, Christopher T. Clarke
Real Time Tracking of Camera Motion Through Cylindrical Passages. DSP (2007)
Kugan Vivekanandarajah, Thambipillai Srikanthan, Christopher T. Clarke
Profile Directed Instruction Cache Tuning for Embedded Systems. ISVLSI (2006)
Siew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke
Rapid generation of custom instructions using predefined dataflow structures. Microprocess. Microsystems 30 (6) (2006)
Suchitra Sathyanarayana, S. Sukthankar, Thambipillai Srikanthan, Christopher T. Clarke
Elimination of sign precomputation in flat CORDIC. ISCAS (4) (2005)
Kugan Vivekanandarajah, Thambipillai Srikanthan, Christopher T. Clarke, Saurav Bhattacharyya
Static Pattern Predictor (SPP) Based Low Power Instruction Cache Design. Embedded Systems and Applications (2003)
M. Bhardwaj, Thambipillai Srikanthan, Christopher T. Clarke
+1}. IEEE Symposium on Computer Arithmetic (1999)
M. Bhardwaj, Thambipillai Srikanthan, Christopher T. Clarke
VLSI Costs of Arithmetic Parallelism: A Residue Reverse Conversion Perspectiv. IEEE Symposium on Computer Arithmetic (1999)
Aniruddha A. Deodhar, Manish Bhardwaj, Christopher T. Clarke, Thambipillai Srikanthan
Designing efficient residue arithmetic based VLSI correlators. ICASSP (1998)