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Arish S
ORCID
Publication Activity (10 Years)
Years Active: 2017-2019
Publications (10 Years): 5
Top Topics
Instruction Set
Intellectual Property
Sparse Matrices
Clef Ip
Top Venues
CoRR
Circuits Syst. Signal Process.
ISVLSI
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Publications
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Arish S
,
R. K. Sharma
Run-time reconfigurable multi-precision floating point multiplier design for high speed, low-power applications.
CoRR
(2019)
Arish S
,
R. K. Sharma
Run-Time-Reconfigurable Multi-Precision Floating-Point Matrix Multiplier Intellectual Property Core on FPGA.
CoRR
(2019)
Arish S
,
Sharad Sinha
,
Smitha K. G.
Optimization of Convolutional Neural Networks on Resource Constrained Devices.
ISVLSI
(2019)
Arish S
,
R. K. Sharma
An efficient floating point multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm.
CoRR
(2019)
Arish S
,
R. K. Sharma
Run-Time-Reconfigurable Multi-Precision Floating-Point Matrix Multiplier Intellectual Property Core on FPGA.
Circuits Syst. Signal Process.
36 (3) (2017)