Run-Time-Reconfigurable Multi-Precision Floating-Point Matrix Multiplier Intellectual Property Core on FPGA.
Arish SR. K. SharmaPublished in: CoRR (2019)
Keyphrases
- floating point
- intellectual property
- square root
- hardware implementation
- sparse matrices
- field programmable gate array
- low cost
- fixed point
- patent search
- digital signal
- systolic array
- clef ip
- patent information
- instruction set
- reconfigurable hardware
- signal processing
- patent documents
- image processing
- floating point arithmetic
- power reduction
- singular value decomposition
- general purpose
- state space
- probabilistic model