Run-Time-Reconfigurable Multi-Precision Floating-Point Matrix Multiplier Intellectual Property Core on FPGA.
Arish SR. K. SharmaPublished in: Circuits Syst. Signal Process. (2017)
Keyphrases
- floating point
- intellectual property
- square root
- hardware implementation
- field programmable gate array
- sparse matrices
- fixed point
- low cost
- patent search
- digital signal
- clef ip
- systolic array
- instruction set
- fast fourier transform
- patent documents
- reconfigurable hardware
- patent information
- floating point arithmetic
- e government
- general purpose
- graphics processing units
- singular value decomposition
- state space
- dynamic programming
- reinforcement learning
- information systems