Run-time reconfigurable multi-precision floating point multiplier design for high speed, low-power applications.
Arish SR. K. SharmaPublished in: CoRR (2019)
Keyphrases
- low power
- high speed
- floating point
- low cost
- single chip
- low power consumption
- logic circuits
- vlsi architecture
- power consumption
- digital signal processing
- power reduction
- gate array
- cmos technology
- power dissipation
- fixed point
- mixed signal
- ultra low power
- high power
- real time
- embedded systems
- nm technology
- instruction set
- wireless transmission
- hardware implementation
- hardware and software
- sparse matrices
- design process