Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis.
Sharad SinhaThambipillai SrikanthanPublished in: Int. J. Reconfigurable Comput. (2014)
Keyphrases
- high level synthesis
- parallel architecture
- management system
- systolic array
- signal processing
- fpga technology
- seamless integration
- high speed
- real time image processing
- hardware design
- digital signal processors
- resource manager
- data processing
- digital signal processing
- real time
- field programmable gate array
- parallel processing
- fpga device
- scheduling problem
- wireless sensor networks
- information systems