Ze-ke Wang

Publication Activity (10 Years)

Years Active: 1984-2022
Publications (10 Years): 15

Top Topics

Data Partitioning

Parallel Algorithm

Fpga Implementation

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Parallel Distributed Syst.

Publications

Jiantong Jiang, Zeyi Wen, Ze-ke Wang, Bingsheng He, Jian Chen
Parallel and Distributed Structured SVM Training. IEEE Trans. Parallel Distributed Syst. 33 (5) (2022)
Ze-ke Wang, Xue Liu, Kai Zhang, Haihang Zhou, Bingsheng He
Understanding and Optimizing Conjunctive Predicates Under Memory-Efficient Storage Layouts. IEEE Trans. Knowl. Data Eng. 33 (6) (2021)
Ze-ke Wang, Kai Zhang, Haihang Zhou, Xue Liu, Bingsheng He
Hebe: An Order-Oblivious and High-Performance Execution Scheme for Conjunctive Predicates. ICDE (2018)
Kai Zhang, Bingsheng He, Jiayu Hu, Ze-ke Wang, Bei Hua, Jiayi Meng, Lishan Yang
G-NET: Effective GPU Sharing in NFV Systems. NSDI (2018)
Xue Liu, Ze-ke Wang, Qingxu Deng
FPGA implementation of a reconfigurable channelization for simultaneous multichannel DRM30/FM receiver. IEEE Trans. Consumer Electron. 63 (1) (2017)
Ze-ke Wang, Johns Paul, Bingsheng He, Wei Zhang
Multikernel Data Partitioning With Channel on OpenCL-Based FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 25 (6) (2017)
Xue Liu, Xin-Xin Yan, Ze-ke Wang, Qingxu Deng
Design and FPGA Implementation of a Reconfigurable Digital Down Converter for Wideband Applications. IEEE Trans. Very Large Scale Integr. Syst. 25 (12) (2017)
Xue Liu, Ze-ke Wang, Qing-xu Deng
Design and FPGA Implementation of a Reconfigurable 1024-Channel Channelization Architecture for SDR Application. IEEE Trans. Very Large Scale Integr. Syst. 24 (7) (2016)
Ze-ke Wang, Johns Paul, Hui Yan Cheah, Bingsheng He, Wei Zhang
Relational query processing on OpenCL-based FPGAs. FPL (2016)
Ze-ke Wang, Bingsheng He, Wei Zhang, Shunning Jiang
A performance analysis framework for optimizing OpenCL applications on FPGAs. HPCA (2016)
Ze-ke Wang, Hui Yan Cheah, Johns Paul, Bingsheng He, Wei Zhang
Accelerating Database Query Processing on OpenCL-based FPGAs (Abstract Only). FPGA (2016)
Ze-ke Wang, Shuhao Zhang, Bingsheng He, Wei Zhang
Melia: A MapReduce Framework on OpenCL-Based FPGAs. IEEE Trans. Parallel Distributed Syst. 27 (12) (2016)
Ze-ke Wang, Bingsheng He, Wei Zhang
Improving Data Partitioning Performance on OpenCL-Based FPGAs. FCCM (2015)
Ze-ke Wang, Bingsheng He, Wei Zhang
A study of data partitioning on OpenCL-based FPGAs. FPL (2015)
Ze-ke Wang, Xue Liu, Bingsheng He, Feng Yu
A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT. IEEE Trans. Very Large Scale Integr. Syst. 23 (5) (2015)
Xue Liu, Qing-xu Deng, Bo-ning Hou, Ze-ke Wang
High-speed, fixed-latency serial links with Xilinx FPGAs. J. Zhejiang Univ. Sci. C 15 (2) (2014)
Ze-ke Wang, Feng Yu, Xue Liu
Block Processor: A resource-distributed architecture. HPEC (2013)
Feng Yu, Rui-feng Ge, Ze-ke Wang
Efficient Utilization of Vector Registers to Improve FFT Performance on SIMD Microprocessors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2013)
Xue Liu, Feng Yu, Ze-ke Wang
A pipelined architecture for normal I/O order FFT. J. Zhejiang Univ. Sci. C 12 (1) (2011)
Zhen-guo Ma, Feng Yu, Rui-feng Ge, Ze-ke Wang
An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays. J. Zhejiang Univ. Sci. C 12 (4) (2011)
Harold W. Kuhn, Ze-ke Wang, Senlin Xu
On the cost of computing roots of polynomials. Math. Program. 28 (2) (1984)