A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks.
Zhibin XiaoBevan M. BaasPublished in: VLSI-SoC (Selected Papers) (2012)
Keyphrases
- high speed
- level parallelism
- multithreading
- single chip
- instruction set
- interconnection networks
- functional units
- real time
- parallel architecture
- small world
- ibm eservertm
- analog vlsi
- high bandwidth
- vlsi implementation
- floating point arithmetic
- low power
- network on chip
- ibm zenterprise
- complex networks
- multi processor
- floating point
- social networks
- systolic array
- industry standard
- ibm power processor
- memory subsystem
- processor core
- memory access
- network structure
- low cost
- embedded dram
- chip design
- fully connected
- processing elements
- random access memory
- power dissipation
- clock frequency
- host computer
- parallel computing
- high density
- functional verification
- parallel processing
- end to end
- computer architecture
- input output
- resource manager
- cmos technology