Zhiyi Yu

ORCID

Publication Activity (10 Years)

Years Active: 1998-2024
Publications (10 Years): 76

Top Venues

ICTA

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Circuits Syst. II Express Briefs

IEICE Electron. Express

Publications

Zhiyi Yu, Hong Li, Jialin Feng
Enhancing text classification with attention matrices based on BERT. Expert Syst. J. Knowl. Eng. 41 (3) (2024)
Zhiyi Yu, Hong Li, Jialin Feng
Contrastive learning for unsupervised sentence embeddings using negative samples with diminished semantics. J. Supercomput. 80 (4) (2024)
Huiyao Wang, Shanlin Xiao, Lingfeng Zhou, Jinghai Wang, Zeyang Xu, Bohan Wang, Zhiyi Yu
LAC: A Novel Lightweight Asynchronous Controller With Optimized Phase Shift. IEEE Trans. Circuits Syst. II Express Briefs 71 (8) (2024)
Lingfeng Zhou, Shanlin Xiao, Huiyao Wang, Jinghai Wang, Zeyang Xu, Bohan Wang, Zhiyi Yu
Better-Than-Worst-Case: A Frequency Adaptation Asynchronous RISC-V Core With Vector Extension. IEEE Trans. Very Large Scale Integr. Syst. 32 (6) (2024)
Wanyuan Pan, Yihe Yu, Chengcheng Tang, Ningyuan Yin, Zhiyi Yu
Low-Power, High-Speed, and Area-Efficient Multiplier Based on the PTL Logic Style. IEEE Trans. Circuits Syst. II Express Briefs 71 (7) (2024)
Jialin Feng, Hong Li, Zhiyi Yu
Enhancing aspect-based sentiment analysis with dependency-attention GCN and mutual assistance mechanism. J. Intell. Inf. Syst. 62 (1) (2024)
Lingfeng Zhou, Shanlin Xiao, Huiyao Wang, Jinghai Wang, Zeyang Xu, Bohan Wang, Zhiyi Yu
An Efficient Asynchronous Circuits Design Flow with Backward Delay Propagation Constraint. DATE (2024)
Yue Liu, Shanlin Xiao, Bo Li, Zhiyi Yu
Sparsespikformer: A Co-Design Framework for Token and Weight Pruning in Spiking Transformer. ICASSP (2024)
Xing Jin, Ningyuan Yin, Weichong Chen, Ximing Li, Guihua Zhao, Zhiyi Yu
A 6T-3M SOT-MRAM for in-memory computing with reconfigurable arithmetic operations. IEICE Electron. Express 20 (11) (2023)
Baiqing Zhong, Mingyu Wang, Chuanghao Zhang, Yangzhan Mai, Xiaojie Li, Zhiyi Yu
A Digital SRAM Computing-in-Memory Design Utilizing Activation Unstructured Sparsity for High-Efficient DNN Inference. ISVLSI (2023)
Wangguang Wang, Mingyu Wang, Yicong Zhang, Yukun Wei, Zhiyi Yu
LWSDP: Locality-Aware Warp Scheduling and Dynamic Data Prefetching Co-design in the Per-SM Private Cache of GPGPUs. ICPADS (2023)
Guihua Zhao, Yating Peng, Yizhan Wang, Caihua Wan, Xianping Liu, Yu Zhang, Xiufeng Han, Weichong Chen, Zhiyi Yu
Computing Resistance-Style Image Sensors for Artificial Neural Networks. IEEE Internet Things J. 10 (6, March 15) (2023)
Jiahua Yan, Mingyu Wang, Yao Qin, Zhiyi Yu
CRAFT: Common Router Architecture for Throughput Optimization. ICA3PP (3) (2023)
Xing Jin, Weichong Chen, Ximing Li, Ningyuan Yin, Caihua Wan, Mingkun Zhao, Xiufeng Han, Zhiyi Yu
High-Reliability, Reconfigurable, and Fully Non-volatile Full-Adder Based on SOT-MTJ for Image Processing Applications. IEEE Trans. Circuits Syst. II Express Briefs 70 (2) (2023)
Kexin Huang, Wei Liu, Yue Liu, Shanlin Xiao, Zhiyi Yu
Towards Efficient On-Chip Learning for Spiking Neural Networks Accelerator with Surrogate Gradient. ICTA (2023)
Xiangyu Meng, Kangfeng Wei, Zhiyi Yu, Xinlun Cai
A Low Power 100-Gb/s PAM-4 Driver with Linear Distortion Compensation in 65-nm CMOS. IEICE Trans. Electron. 106 (1) (2023)
Yicong Zhang, Mingyu Wang, Wangguang Wang, Zhiyi Yu
Re-Cache: Mitigating cache contention by exploiting locality characteristics with reconfigurable memory hierarchy for GPGPUs. Microelectron. J. 138 (2023)
Jilong Luo, Shanlin Xiao, Yinsheng Chen, Zhiyi Yu
Enabling energy-Efficient object detection with surrogate gradient descent in spiking neural networks. CoRR (2023)
Chuanghao Zhang, Mingyu Wang, Yangzhan Mai, Chengcheng Tang, Zhiyi Yu
A High-Density and Reconfigurable SRAM-Based Digital Compute-In-Memory Macro for Low-Power AI Chips. IEEE Trans. Circuits Syst. II Express Briefs 70 (9) (2023)
Yicong Zhang, Mingyu Wang, Yangzhan Mai, Zhiyi Yu
TensorCache: Reconstructing Memory Architecture With SRAM-Based In-Cache Computing for Efficient Tensor Computations in GPGPUs. IEEE Trans. Very Large Scale Integr. Syst. 31 (12) (2023)
Xiaoran Zhang, Mingyu Wang, Yicong Zhang, Tao Lu, Zhiyi Yu
A Scalable Deadlock-Free Static Routing Algorithm for Chiplet-Based Systems. ICPADS (2023)
Zeyang Xu, Shanlin Xiao, Lingfeng Zhou, Bohan Wang, Zhiyi Yu
Towards Energy-Efficient Asynchronous Circuit Design with Flip-Flop-to-Latch Replacement. ICTA (2023)
Ximing Li, Xing Jin, Weichong Chen, Ningyuan Yin, Zhiyi Yu
Parallel-Prefix Adder in Spin-Orbit Torque Magnetic RAM for High Bit-Width Non-Volatile Computation. IEEE Trans. Circuits Syst. II Express Briefs 70 (2) (2023)
Yangzhan Mai, Mingyu Wang, Chuanghao Zhang, Baiqing Zhong, Zhiyi Yu
A 1.97 TFLOPS/W Configurable SRAM-Based Floating-Point Computation-in-Memory Macro for Energy-Efficient AI Chips. ISCAS (2023)
Yue Liu, Shanlin Xiao, Bo Li, Zhiyi Yu
SparseSpikformer: A Co-Design Framework for Token and Weight Pruning in Spiking Transformer. CoRR (2023)
Xiangyu Meng, Yecong Li, Zhiyi Yu
A Low Insertion Loss Wideband Bonding-Wire Based Interconnection for 400 Gbps PAM4 Transceivers. IEICE Trans. Electron. 106 (1) (2023)
Zhiyi Yu, Chao Li, Chaochen Hu, Zhen Chen, Yandong Yao, Jiang Wu, Hao Wang, Jialun Du, Min Guo, Haoyu Wang, Weimin Li, Xiu Li, Xiaodong Ma, Yisong Zhangi, Shuangshou Li
One Case of THOUGHT: Industry-University Converged Education Practice on Open Source. ICCSE (3) (2022)
Huafeng Ye, Huipeng Deng, Jian Wang, Mingyu Wang, Zhiyi Yu
3D-NWA: A Nested-Winograd Accelerator for 3D CNNs. ICTA (2022)
Sheng Zuo, Junjie Zhuang, Yao Liu, Mingyu Wang, Zhiyi Yu
Hardware Based RISC-V Instruction Set Randomization. ICTA (2022)
Ruimin Zhu, Zeyang Xu, Yuhao Huang, Shanlin Xiao, Zhiyi Yu
DFT Architecture for Click-Based Bundled-Data Asynchronous Circuits. ICTA (2022)
Guihua Zhao, Xing Jin, Huafeng Ye, Yating Peng, Wei Liu, Ningyuan Yin, Weichong Chen, Jianjun Chen, Ximing Li, Zhiyi Yu
An in-memory computing multiply-and-accumulate circuit based on ternary STT-MRAMs for convolutional neural networks. IEICE Electron. Express 19 (20) (2022)
Wenzha Yang, Yong Ma, Jiajie Yan, Yang Chen, Shanlin Xiao, Zhiyi Yu
A dual-rail/single-rail hybrid system using null convention logic circuits. Microelectron. J. 125 (2022)
Yuhao Huang, Shanlin Xiao, Zhiyu Li, Zhiyi Yu
An Asynchronous Bundled-Data Template With Current Sensing Completion Detection Technique. IEEE Trans. Circuits Syst. II Express Briefs 69 (9) (2022)
Qingyi Xie, Ziyuan Luo, Shanlin Xiao, Kai Wang, Zhiyi Yu
High-Throughput Zipper Encoder for 800G Optical Communication System. ICTA (2021)
Zhiyu Li, Yuhao Huang, Longfeng Tian, Ruimin Zhu, Shanlin Xiao, Zhiyi Yu
A Low-Power Asynchronous RISC-V Processor With Propagated Timing Constraints Method. IEEE Trans. Circuits Syst. II Express Briefs 68 (9) (2021)
Shanlin Xiao, Weikun Liu, Junshu Lin, Zhiyi Yu
A Data-Driven Asynchronous Neural Network Accelerator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (9) (2021)
Jian Wang, Huipeng Deng, Huafeng Ye, Shanlin Xiao, Zhiyi Yu
FWUA : A Flexible Winograd-Based Uniform Accelerator for 1D/2D/3D CNNs. ICTA (2021)
Mingyuan Meng, Xingyu Yang, Lei Bi, Jinman Kim, Shanlin Xiao, Zhiyi Yu
High-parallelism Inception-like Spiking Neural Networks for Unsupervised Feature Learning. Neurocomputing 441 (2021)
Ningyuan Yin, Baofa Huang, Xiaobai Chen, Jianjun Chen, Zhiyi Yu
An MTJ-Based Asynchronous System With Extremely Fine-Grained Voltage Scaling. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (1) (2021)
Bin Zheng, Zhengbao Lei, Chen Tang, Jin Wang, Zhuofan Liao, Zhiyi Yu, Yiming Xie
OERFF: A Vehicle Re-Identification Method Based on Orientation Estimation and Regional Feature Fusion. IEEE Access 9 (2021)
Ziyuan Luo, Qingyi Xie, Shanlin Xiao, Zhiyi Yu
A high throughput spatially coupled low density generator matrix coding system. ICTA (2021)
Huipeng Deng, Jian Wang, Huafeng Ye, Shanlin Xiao, Xiangyu Meng, Zhiyi Yu
3D-VNPU: A Flexible Accelerator for 2D/3D CNNs on FPGA. FCCM (2021)
Qiang Zhang, Shanlin Xiao, Zhiyi Yu, Huanliang Zheng, Peng Wang
Hand gesture recognition algorithm combining hand-type adaptive algorithm and effective-area ratio for efficient edge computing. J. Electronic Imaging 30 (6) (2021)
Huanliang Zheng, Yuhao Guo, Xingyu Yang, Shanlin Xiao, Zhiyi Yu
Balancing the Cost and Performance Trade-Offs in SNN Processors. IEEE Trans. Circuits Syst. II Express Briefs 68 (9) (2021)
Huipeng Deng, Jian Wang, Huafeng Ye, Shanlin Xiao, Xiangyu Meng, Zhiyi Yu
Dimension fusion: Dimension-level dynamically composable accelerator for convolutional neural networks. IEICE Electron. Express 18 (24) (2021)
Mingyuan Meng, Xingyu Yang, Shanlin Xiao, Zhiyi Yu
Spiking Inception Module for Multi-layer Unsupervised Spiking Neural Networks. CoRR (2020)
Xingyu Yang, Mingyuan Meng, Shanlin Xiao, Zhiyi Yu
SPA: Stochastic Probability Adjustment for System Balance of Unsupervised SNNs. ICPR (2020)
Shanlin Xiao, Wei Liu, Yuhao Guo, Zhiyi Yu
Low-Cost Adaptive Exponential Integrate-and-Fire Neuron Using Stochastic Computing. IEEE Trans. Biomed. Circuits Syst. 14 (5) (2020)
Wenkang Liao, Yuhao Guo, Shanlin Xiao, Zhiyi Yu
A Low-Cost and High-Throughput NoC-Aware Chip-to-Chip Interconnection. ISCAS (2020)
Shanlin Xiao, Yuhao Guo, Wenkang Liao, Huipeng Deng, Yi Luo, Huanliang Zheng, Jian Wang, Cheng Li, Gezi Li, Zhiyi Yu
NeuronLink: An Efficient Chip-to-Chip Interconnect for Large-Scale Neural Network Accelerators. IEEE Trans. Very Large Scale Integr. Syst. 28 (9) (2020)
Weikun Liu, Junshu Lin, Xusheng Li, Shanlin Xiao, Zhiyi Yu
A Low-Power Processing Element Based on Asynchronous Data-Driven Bit-Serial Multiplier for CNNs. ICTA (2020)
Xingyu Yang, Mingyuan Meng, Shanlin Xiao, Zhiyi Yu
SPA: Stochastic Probability Adjustment for System Balance of Unsupervised SNNs. CoRR (2020)
Mingyuan Meng, Xingyu Yang, Shanlin Xiao, Zhiyi Yu
Spiking Inception Module for Multi-layer Unsupervised Spiking Neural Networks. IJCNN (2020)
Junshu Lin, Weikun Liu, Xusheng Li, Shanlin Xiao, Zhiyi Yu
An Asynchronous Convolution Process Engine forVGG-16 Neural Network. ICTA (2020)
Jianmin Zeng, Zhang Zhang, Runhao Chen, Shiyue Liang, Tianlin Cao, Zhiyi Yu, Xin Cheng, Guangjun Xie
DM-IMCA: A dual-mode in-memory computing architecture for general purpose processing. IEICE Electron. Express 17 (4) (2020)
Mingyuan Meng, Xingyu Yang, Shanlin Xiao, Zhiyi Yu
BioSNet: A Fast-Learning and High-Robustness Unsupervised Biomimetic Spiking Neural Network. CoRR (2020)
Xiaobai Chen, Jinglong Xu, Zhiyi Yu
A 68-mw 2.2 Tops/w Low Bit Width and Multiplierless DCNN Object Detection Processor for Visually Impaired People. IEEE Trans. Circuits Syst. Video Technol. 29 (11) (2019)
Ming-e Jing, Yujie Huang, Yibo Fan, Xiaoyong Xue, Xiaoyang Zeng, Zhiyi Yu
An Automatic Task Partition Method for Multi-core System. ISCAS (2018)
Xiaobai Chen, Zhiyi Yu
A Flexible and Energy-Efficient Convolutional Neural Network Acceleration With Dedicated ISA and Accelerator. IEEE Trans. Very Large Scale Integr. Syst. 26 (7) (2018)
Xiaobai Chen, Shanlin Xiao, Zhiyi Yu
A Reconfigurable Process Engine for Flexible Convolutional Neural Network Acceleration. APSIPA (2018)
Weijing Shi, Xin Li, Zhiyi Yu, Gary Overett
An FPGA-Based Hardware Accelerator for Traffic Sign Detection. IEEE Trans. Very Large Scale Integr. Syst. 25 (4) (2017)
Jianmin Zeng, Chubin Wu, Zhang Zhang, Xin Cheng, Guangjun Xie, Jun Han, Xiaoyang Zeng, Zhiyi Yu
A multi-core-based heterogeneous parallel turbo decoder. IEICE Electron. Express 14 (18) (2017)
Sai Manoj P. D., Jie Lin, Shikai Zhu, Yingying Yin, Xu Liu, Xiwei Huang, Chongshen Song, Wenqi Zhang, Mei Yan, Zhiyi Yu, Hao Yu
A Scalable Network-on-Chip Microprocessor With 2.5D Integrated Memory and Accelerator. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2017)
Baofa Huang, Ningyuan Yin, Zhiyi Yu
The write deduplication mechanism based on a novel low-power data latched sense amplifier for a magnetic tunnel junction based non-volatile memory. ASICON (2017)
Jianwei Yang, Weizhen Wang, Zhicheng Xie, Jun Han, Zhiyi Yu, Xiaoyang Zeng
Parallel implementations of SHA-3 on a 24-core processor with software and hardware co-design. ASICON (2017)
Xiaobai Chen, Jinlong Xu, Zhiyi Yu
A fast and energy efficient FPGA-based system for real-time object tracking. APSIPA (2017)
Xiaoyang Zeng, Yi Li, Yuejun Zhang, Shujie Tan, Jun Han, Xingxing Zhang, Zhang Zhang, Xu Cheng, Zhiyi Yu
Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process. IEEE Trans. Very Large Scale Integr. Syst. 23 (7) (2015)
Jianming Yu, Wei Zhou, Yueming Yang, Xiaodong Zhang, Zhiyi Yu
Many-Core Processors Granularity Evaluation by Considering Performance, Yield, and Lifetime Reliability. IEEE Trans. Very Large Scale Integr. Syst. 23 (10) (2015)
Jielin Wang, Weizhen Wang, Jianwei Yang, Zhiyi Yu, Jun Han, Xiaoyang Zeng
Parallel implementation of AES on 2.5D multicore platform with hardware and software co-design. ASICON (2015)
Yi Ren, Jun Han, Zhiyi Yu, Sizhong Xuan, Xiaoyang Zeng
A lifting-based 2-D discrete wavelet transform architecture for data compression of bio-potential signals. ASICON (2015)
Yawei Guo, Yue Wu, Dongdong Guo, Xu Cheng, Zhiyi Yu, Xiaoyang Zeng
Non-binary digital calibration for split-capacitor DAC in SAR ADC. IEICE Electron. Express 12 (4) (2015)
Masoud Daneshtalab, Farhad Mehdipour, Zhiyi Yu, Hannu Tenhunen
Special Issue on Emerging Many-Core Systems for Exascale Computing. ACM J. Emerg. Technol. Comput. Syst. 11 (4) (2015)
Sizhong Xuan, Jun Han, Zhiyi Yu, Yi Ren, Xiaoyang Zeng
A configurable SoC design for information security. ASICON (2015)
Jie Lin, Shikai Zhu, Zhiyi Yu, Dongjun Xu, Sai Manoj P. D., Hao Yu
A scalable and reconfigurable 2.5D integrated multicore processor on silicon interposer. CICC (2015)
Jun Han, Yang Li, Zhiyi Yu, Xiaoyang Zeng
A 65 nm Cryptographic Processor for High Speed Pairing Computation. IEEE Trans. Very Large Scale Integr. Syst. 23 (4) (2015)
Jun Han, Renfeng Dou, Lingyun Zeng, Shuai Wang, Zhiyi Yu, Xiaoyang Zeng
A Heterogeneous Multicore Crypto-Processor With Flexible Long-Word-Length Computation. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2015)
Lijun Zhou, Zhiyi Yu, Jie Lin, Shikai Zhu, Weijing Shi, Haijie Zhou, Kunpeng Song, Xiaoyang Zeng
Acceleration of Naive-Bayes algorithm on multicore processor for massive text classification. ISIC (2014)
Zhiyi Yu, Ruijin Xiao, Kaidi You, Heng Quan, Peng Ou, Zheng Yu, Maofei He, Jiajie Zhang, Yan Ying, Haofan Yang, Jun Han, Xu Cheng, Zhang Zhang, Ming-e Jing, Xiaoyang Zeng
A 16-Core Processor With Shared-Memory and Message-Passing Communications. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2014)
Zheng Yu, Zhiyi Yu, Xueqiu Yu, Ningxi Liu, Xiaoyang Zeng
Low-Power Multicore Processor Design With Reconfigurable Same-Instruction Multiple Process. IEEE Trans. Circuits Syst. II Express Briefs (6) (2014)
Renfeng Dou, Jun Han, Yifan Bo, Zhiyi Yu, Xiaoyang Zeng
An Efficient Implementation of Montgomery Multiplication on Multicore Platform With Optimized Algorithm, Task Partitioning, and Network Architecture. IEEE Trans. Very Large Scale Integr. Syst. 22 (11) (2014)
Yi Li, Liang Wen, Yuejun Zhang, Xu Cheng, Jun Han, Zhiyi Yu, Xiaoyang Zeng
An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing. IEICE Electron. Express 11 (3) (2014)
Jun Han, Shuai Wang, Wei Huang, Zhiyi Yu, Xiaoyang Zeng
Parallelization of Radix-2 Montgomery Multiplication on Multicore Platform. IEEE Trans. Very Large Scale Integr. Syst. 21 (12) (2013)
Qing Zhang, Xueqiu Yu, Zhiyi Yu, Xiaoyang Zeng
A turbo decoder implementation for LTE downlink mapped on a multi-core processor platform. ASICON (2013)
Peng Ou, Jiajie Zhang, Heng Quan, Yi Li, Maofei He, Zheng Yu, Xueqiu Yu, Shile Cui, Jie Feng, Shikai Zhu, Jie Lin, Ming-e Jing, Xiaoyang Zeng, Zhiyi Yu
A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array. ISSCC (2013)
Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng, Liyang Zhou
Time-Division-Multiplexer based routing algorithm for NoC system. ISCAS (2013)
Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng, Jiayi Sheng, Haofan Yang
Implementation and optimization of 3780-point FFT on multi-core system. ISCAS (2013)
Zongyan Wang, Dexue Zhang, Xueqiu Yu, Zhiyi Yu, Xiaoyang Zeng
A fast multi-core virtual platform and its application on software development. ASICON (2013)
Jie Lin, Wei Zhou, Zhiyi Yu, Xiaoyang Zeng
A hybrid router combining circuit switching and packet switching with virtual channels for on-chip networks. ASICON (2013)
Pengjun Wang, Yuejun Zhang, Jun Han, Zhiyi Yu, Yibo Fan, Zhang Zhang
Architecture and Physical Implementation of Reconfigurable Multi-Port Physical Unclonable Functions in 65 nm CMOS. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (5) (2013)
Haofan Yang, Kedong Chen, Shengqiong Xie, Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng
Efficient implementation of 3780-point FFT on a 16-core processor. ASICON (2013)
Wei Zhou, Jianming Yu, Jie Lin, Zhiyi Yu, Xiaoyang Zeng
A 2D mesh NoC with self-configurable and shared-FIFOs routers. ASICON (2013)
Zheng Yu, Jiajie Zhang, Xueqiu Yu, Xiaoyang Zeng, Zhiyi Yu
A low power register file with asynchronously controlled read-isolation and software-directed write-discarding. ISCAS (2013)
Jiajie Zhang, Zheng Yu, Zhiyi Yu, Kexin Zhang, Zhonghai Lu, Axel Jantsch
Efficient distributed memory management in a multi-core H.264 decoder on FPGA. ISSoC (2013)
Shikai Zhu, Zheng Yu, Shile Cui, Zhiyi Yu, Xiaoyang Zeng
H.264 video parallel decoder on a 24-core processor. ASICON (2013)
Jun Han, Xingxing Zhang, Yi Li, Baoyu Xiong, Yuejun Zhang, Zhang Zhang, Zhiyi Yu, Xu Cheng, Xiaoyang Zeng
A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS. IEICE Electron. Express 9 (16) (2012)
Zhiyi Yu, Kaidi You, Ruijin Xiao, Heng Quan, Peng Ou, Yan Ying, Haofan Yang, Ming-e Jing, Xiaoyang Zeng
An 800MHz 320mW 16-core processor with message-passing and shared-memory inter-core communication mechanisms. ISSCC (2012)
Wenhua Fan, Chen Chen, Yun Chen, Zhiyi Yu, Xiaoyang Zeng
Efficient Implementation of OFDM Inner Receiver on a Programmable Multi-Core Processor Platform. IEICE Trans. Commun. (4) (2012)
Yuejun Zhang, Pengjun Wang, Baoyu Xiong, Zhiyi Yu
Design of a high information-density multiple valued 2-read 1-write register file. IEICE Electron. Express 9 (11) (2012)
Bei Huang, Kaidi You, Yun Chen, Zhiyi Yu, Xiaoyang Zeng
A Fully Programmable Reed-Solomon Decoder on a Multi-Core Processor Platform. IEICE Trans. Inf. Syst. (12) (2012)
Liyang Zhou, Ming-e Jing, Liulin Zhong, Zhiyi Yu, Xiaoyang Zeng
Task-binding based branch-and-bound algorithm for NoC mapping. ISCAS (2012)

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Publication Activity (10 Years)

Top Topics

Top Venues

Zhiyi Yu