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An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing.
Yi Li
Liang Wen
Yuejun Zhang
Xu Cheng
Jun Han
Zhiyi Yu
Xiaoyang Zeng
Published in:
IEICE Electron. Express (2014)
Keyphrases
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low voltage
cost effective
high speed
design process
low power
data flow
data transmission
power line