Jun Han

ORCID

Publication Activity (10 Years)

Years Active: 2006-2024
Publications (10 Years): 66

Top Venues

ASICON

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Circuits Syst. II Express Briefs

ISCAS

Publications

Jiawei Wang, Zhao Gao, Xu Cheng, Jue Wang, Zhen Li, Jun Han, Xiaoyang Zeng
A 1.6 GS/s 42.6-dB SNDR Synthesis Friendly Time-Interleaved SAR ADC Using Metastability Detection and Escape Acceleration Technique. IEEE Trans. Circuits Syst. II Express Briefs 71 (4) (2024)
Lizhou Wu, Chenyang Zhao, Jingbo Wang, Xueru Yu, Shoumian Chen, Chen Li, Jun Han, Xiaoyong Xue, Xiaoyang Zeng
A Heuristic and Greedy Weight Remapping Scheme with Hardware Optimization for Irregular Sparse Neural Networks Implemented on CIM Accelerator in Edge AI Applications. ASPDAC (2024)
Zikang Zhou, Xuyang Duan, Kaiqi Chen, Yaqi Chen, Jun Han
ML-Fusion: Determining Memory Levels for Data Reuse Between DNN Layers. ACM Great Lakes Symposium on VLSI (2024)
Xinglong Yu, Yi Sun, Yifan Zhao, Honglin Kuang, Jun Han
RVCE-FAL: A RISC-V Scalar-Vector Custom Extension for Faster FALCON Digital Signature. DATE (2024)
Zhen Li, Jing Wang, Man-Kay Law, Sijun Du, Junrui Liang, Xu Cheng, Jun Han, Xiaoyang Zeng, Zhiyuan Chen
Piezoelectric Energy Harvesting Interface Using Self-Bias-Flip Rectifier and Switched-PEH DC-DC for MPPT. IEEE J. Solid State Circuits 59 (7) (2024)
Yongliang Zhang, Yitong Rong, Xuyang Duan, Zhen Yang, Qiang Li, Ziyu Guo, Xu Cheng, Xiaoyang Zeng, Jun Han
An Energy-Efficient BNN Accelerator With Two-Stage Value Prediction for Sparse-Edge Gesture Recognition. IEEE Trans. Circuits Syst. I Regul. Pap. 71 (1) (2024)
Zikang Zhou, Xuyang Duan, Jun Han
A Design Framework for Generating Energy-Efficient Accelerator on FPGA Toward Low-Level Vision. IEEE Trans. Very Large Scale Integr. Syst. 32 (8) (2024)
Xinhao Mao, Ziyu Guo, Jun Han, Bo Hu, Xiaoyang Zeng
Hardware Acceleration of Phase and Gain Control for Analog Beamforming. ISCAS (2024)
Yuanyuan Han, Xu Cheng, Xiaoyong Xue, Jun Han, Jiawei Xu, Xiaoyang Zeng
SET Tolerable SRAM Hardened by DMR Circuit With Feedback-Split-Gate Voter and High-Speed Hierarchical Structure. IEEE Trans. Circuits Syst. II Express Briefs 71 (3) (2024)
Yitong Rong, Xuyang Duan, Jun Han
A high-throughput and low-storage stereo vision accelerator with dependency-resolving strided aggregation for 8-path semi-global matching. Microelectron. J. 146 (2024)
Li Wan, Fu Chao, Qiang Li, Jun Han
LockillerTM: Enhancing Performance Lower Bounds in Best-Effort Hardware Transactional Memory. IPDPS (2024)
Song Wang, Xu Cheng, Ziyu Guo, Jun Han
A foreground digital calibration algorithm for time-interleaved ADCs with low computational complexity. Microelectron. J. 136 (2023)
Qiang Li, Jun Tao, Jun Han
SPARK: An automatic Score-Power-Area efficient RISC-V processor microarchitecture SeeKer. Microelectron. J. 132 (2023)
Yifan Zhao, Honglin Kuang, Yi Sun, Zhen Yang, Chen Chen, Jianyi Meng, Jun Han
Enhancing RISC-V Vector Extension for Efficient Application of Post-Quantum Cryptography. ASAP (2023)
Honglin Kuang, Yifan Zhao, Yi Sun, Jun Han
) Polynomial Operation in Post-quantum Cryptography. ASICON (2023)
Baijie Zhang, Jiawei Wang, Xu Cheng, Jun Han, Xiaoyang Zeng
Dominant-Node Theory and Monitoring-Rescue Method for Eliminating Undesired Operating Points in the Self-Biased Reference Generators. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (12) (2023)
Yan Li, Chao Chen, Xu Cheng, Jun Han, Xiaoyang Zeng
DMBF: Design Metrics Balancing Framework for Soft-Error-Tolerant Digital Circuits Through Bayesian Optimization. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (10) (2023)
Yan Liu, Yan Li, Xu Cheng, Jun Han, Xiaoyang Zeng
A Non-Redundant Latch With Key-Node-Upset Obstacle of Beneficial Efficiency for Harsh Environments Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (4) (2023)
Zhen Li, Zhiyuan Chen, Man-Kay Law, Sijun Du, Xu Cheng, Xiaoyang Zeng, Jun Han
A Self Bias-flip Piezoelectric Energy Harvester Array without External Energy Reservoirs achieving 488% Improvement with 4-Ratio Switched-PEH DC-DC Converter. CICC (2023)
Xuyang Duan, Yufan Chen, Menghan Li, Yitong Rong, Ruiqi Xie, Jun Han
UArch: A Super-Resolution Processor With Heterogeneous Triple-Core Architecture for Workloads of U-Net Networks. IEEE Trans. Biomed. Circuits Syst. 17 (3) (2023)
Zengshi Wang, Chao Fu, Jun Han
Coupled Data Prefetch and Cache Partitioning Scheme for CPU-Accelerator System. ASICON (2023)
Yufan Chen, Xuyang Duan, Jun Han
UACT: A Unified Energy-efficient Computing Architecture for CNN and TCNN. ASICON (2023)
Kaixuan Wang, Xinyu Qin, Zhuoyuan Yang, Weiliang He, Yifan Liu, Jun Han
SVP: Safe and Efficient Speculative Execution Mechanism through Value Prediction. ACM Great Lakes Symposium on VLSI (2023)
Jing Wang, Zhiyuan Chen, Junrui Liang, Xu Cheng, Jun Han, Xiaoyang Zeng
A Cross Regulation Reduced Multi-Output and Multi-VCR Piezoelectric Energy Harvesting System Using Shared Capacitors. ISCAS (2022)
Chao Fu, Li Wan, Jun Han
LosaTM: A Hardware Transactional Memory Integrated With a Low-Overhead Scenario-Awareness Conflict Manager. IEEE Trans. Parallel Distributed Syst. 33 (12) (2022)
Jiawei Wang, Jue Wang, Xu Cheng, Jun Han, Xiaoyang Zeng
A Synthesis Friendly Dynamic Amplifier with Fuzzy-Logic Piecewise-Linear Calibration. ISCAS (2022)
Baijie Zhang, Jue Wang, Xu Cheng, Jun Han, Xiaoyang Zeng
An Enhanced Start-up Circuit Eliminating All Trojan States in Self-biased Reference Generators. ISCAS (2022)
Yifan Zhao, Ruiqi Xie, Guozhu Xin, Jun Han
A High-Performance Domain-Specific Processor With Matrix Extension of RISC-V for Module-LWE Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (7) (2022)
Yong-Liang Zhang, Qiang Li, Hui Zhang, Wei-Zhen Wang, Jun Han, Xiaoyang Zeng, Xu Cheng
A 28 nm, 397 μW real-time dynamic gesture recognition chip based on RISC-V processor. Microelectron. J. 116 (2021)
Ruiqi Xie, Jun Yin, Jun Han
DyGA: A Hardware-Efficient Accelerator With Traffic-Aware Dynamic Scheduling for Graph Convolutional Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (12) (2021)
Guozhu Xin, Yifan Zhao, Jun Han
A Multi-Layer Parallel Hardware Architecture for Homomorphic Computation in Machine Learning. ISCAS (2021)
Weizhen Wang, Jun Han, Xu Cheng, Xiaoyang Zeng
An energy-efficient crypto-extension design for RISC-V. Microelectron. J. 115 (2021)
Chiyu Tan, Yan Li, Xu Cheng, Jun Han, Xiaoyang Zeng
General Efficient TMR for Combinational Circuit Hardening Against Soft Errors and Improved Multi-Objective Optimization Framework. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (7) (2021)
Jue Wang, Xu Cheng, Jun Han, Xiaoyang Zeng
Synthesizable lead-lag quantization technique for digital VCO-based ΔΣ ADC. Microelectron. J. 110 (2021)
Ruiqi Xie, Jun Han
Mini-HOG: An Area-efficient and Low-power HOG Accelerator with SW/HW co-design for Real-time Pedestrian Detection. ASICON (2021)
Xinyu Qin, Xudong Liu, Jun Han
A CNN Hardware Accelerator Designed for YOLO Algorithm Based on RISC-V SoC. ASICON (2021)
Xuyang Duan, Ruiqi Xie, Jun Han
An Energy-Efficient Image Denoising Accelerator with Depth-wise Separable Convolution and Fused-Layer Architecture. ASICON (2021)
Yan Li, Jun Han, Xiaoyang Zeng, Mehdi B. Tahoori
TRIGON: A Single-phase-clocking Low Power Hardened Flip-Flop with Tolerance to Double-Node-Upset for Harsh Environments Applications. DATE (2021)
Jun Yin, Jun Han, Ruiqi Xie, Chenghao Wang, Xuyang Duan, Yitong Rong, Xiaoyang Zeng, Jun Tao
MC-LSTM: Real-Time 3D Human Action Detection System for Intelligent Healthcare Applications. IEEE Trans. Biomed. Circuits Syst. 15 (2) (2021)
Jue Wang, Zhenyu Yang, Jiawei Wang, Xu Cheng, Jun Han, Xiaoyang Zeng
VCO-Based Delta Sigma Modulator with Digital Tri-level Feedback Scheme. A-SSCC (2021)
Keji Zhou, Chenyang Zhao, Jinbei Fang, Jingwen Jiang, Deyang Chen, Yujie Huang, Ming-e Jing, Jun Han, Haidong Tian, Xiankui Xiong, Qi Liu, Xiaoyong Xue, Xiaoyang Zeng
An Energy Efficient Computing-in-Memory Accelerator With 1T2R Cell and Fully Analog Processing for Edge AI Applications. IEEE Trans. Circuits Syst. II Express Briefs 68 (8) (2021)
Yuanyuan Han, Tongde Li, Xu Cheng, Liang Wang, Jun Han, Yuanfu Zhao, Xiaoyang Zeng
Radiation Hardened 12T SRAM With Crossbar-Based Peripheral Circuit in 28nm CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (7) (2021)
Yan Li, Xu Cheng, Chiyu Tan, Jun Han, Yuanfu Zhao, Liang Wang, Tongde Li, Mehdi B. Tahoori, Xiaoyang Zeng
A Robust Hardened Latch Featuring Tolerance to Double-Node-Upset in 28nm CMOS for Spaceborne Application. IEEE Trans. Circuits Syst. II Express Briefs (9) (2020)
Jianwei Yang, Jun Han, Fan Dai, Weizhen Wang, Xiaoyang Zeng
A Power Analysis Attack Resistant Multicore Platform With Effective Randomization Techniques. IEEE Trans. Very Large Scale Integr. Syst. 28 (6) (2020)
Xu Cheng, Jue Wang, Jun Han, Xiaoyang Zeng
Design Methodology of Clock Polarity Inversion Technique for Frequency Dividers. ISCAS (2020)
Jue Wang, Xu Cheng, Jun Han, Xiaoyang Zeng
A Synthesis Friendly VCO-Based Delta-Sigma ADC with Process Variation Tolerance. ISCAS (2020)
Guozhu Xin, Jun Han, Tianyu Yin, Yuchao Zhou, Jianwei Yang, Xu Cheng, Xiaoyang Zeng
VPQC: A Domain-Specific Vector Processor for Post-Quantum Cryptography Based on RISC-V Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2020)
Jun Yin, Jun Han, Xiaodong Zhang
An Optimization Toolchain Design of Deep Learning Deployment Based on Heterogeneous Computing Platform. WCSP (2020)
Yuanyuan Han, Xu Cheng, Jun Han, Xiaoyang Zeng
Radiation-Hardened 0.3-0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications. IEEE Trans. Very Large Scale Integr. Syst. 28 (4) (2020)
Yan Li, Xiaoyoung Zeng, Zhengqi Gao, Liyu Lin, Jun Tao, Jun Han, Xu Cheng, Mehdi B. Tahoori, Xiaoyang Zeng
Exploring a Bayesian Optimization Framework Compatible with Digital Standard Flow for Soft-Error-Tolerant Circuit. DAC (2020)
Jun Yin, Jun Han, Chenghao Wang, Bingyi Zhang, Xiaoyang Zeng
A Skeleton-based Action Recognition System for Medical Condition Detection. BioCAS (2019)
Bingyi Zhang, Jun Han, Zhize Huang, Jianwei Yang, Xiaoyang Zeng
A Real-Time and Hardware-Efficient Processor for Skeleton-Based Action Recognition With Lightweight Convolutional Neural Network. IEEE Trans. Circuits Syst. II Express Briefs (12) (2019)
Riyong Zheng, Chenghao Wang, Jun Han, Xiaoyang Zeng
A Hardware-efficient Accelerator for Encoding Stage of Text-to-speech Synthesis. ASICON (2019)
Yujie Huang, Yujie Cai, Ming-e Jing, Jun Han, Yibo Fan, Xiaoyang Zeng
The Hardware Acceleration of SC Decoder for Polar Code towards HLS Optimization. ISOCC (2018)
Bingyi Zhang, Xin Li, Jun Han, Xiaoyang Zeng
MiniTracker: A Lightweight CNN-based System for Visual Object Tracking on Embedded Device. DSL (2018)
Jianwei Yang, Fan Dai, Jielin Wang, Jianmin Zeng, Zhang Zhang, Jun Han, Xiaoyang Zeng
Countering power analysis attacks by exploiting characteristics of multicore processors. IEICE Electron. Express 15 (7) (2018)
Yalong Pang, Ying Zhang, Jun Han, Xiaoyang Zeng
arithmetic acceleration based on modified Barrett modular multiplication algorithm. ASICON (2017)
Jianmin Zeng, Chubin Wu, Zhang Zhang, Xin Cheng, Guangjun Xie, Jun Han, Xiaoyang Zeng, Zhiyi Yu
A multi-core-based heterogeneous parallel turbo decoder. IEICE Electron. Express 14 (18) (2017)
Jianwei Yang, Weizhen Wang, Zhicheng Xie, Jun Han, Zhiyi Yu, Xiaoyang Zeng
Parallel implementations of SHA-3 on a 24-core processor with software and hardware co-design. ASICON (2017)
Ying Zhang, Yujie Huang, Jun Han, Xiaoyang Zeng
FPGA-based efficient implementation of SURF algorithm. ASICON (2017)
Yujie Cai, Xin Li, Jun Han, Xiaoyang Zeng
A configurable nonlinear operation unit for neural network accelerator. ASICON (2017)
Xin Li, Yujie Cai, Jun Han, Xiaoyang Zeng
A high utilization FPGA-based accelerator for variable-scale convolutional neural network. ASICON (2017)
Yalong Pang, Jun Han, Jianmin Zeng, Yujie Huang, Xiaoyang Zeng
Instruction set extension and hardware acceleration for SVM application toward a vector processor. ISOCC (2017)
Jun Han, Yicheng Zhang, Shan Huang, Mengyuan Chen, Xiaoyang Zeng
An Area-Efficient Error-Resilient Ultralow-Power Subthreshold ECG Processor. IEEE Trans. Circuits Syst. II Express Briefs (10) (2016)
Shan Huang, Jun Han, Xin Li, Zongxian Yang, Xiaoyang Zeng
A low-cost and energy-efficient EEG processor for continuous seizure detection using wavelet transform and AdaBoost. BioCAS (2016)
Weizhen Wang, Jun Han, Zhicheng Xie, Shan Huang, Xiaoyang Zeng
Cryptographie coprocessor design for IoT sensor nodes. ISOCC (2016)
Yao Zou, Jun Han, Sizhong Xuan, Shan Huang, Xinqian Weng, Dabin Fang, Xiaoyang Zeng
An Energy-Efficient Design for ECG Recording and R-Peak Detection Based on Wavelet Transform. IEEE Trans. Circuits Syst. II Express Briefs (2) (2015)
Xiaoyang Zeng, Yi Li, Yuejun Zhang, Shujie Tan, Jun Han, Xingxing Zhang, Zhang Zhang, Xu Cheng, Zhiyi Yu
Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process. IEEE Trans. Very Large Scale Integr. Syst. 23 (7) (2015)
Zhicheng Xie, Jun Han, Jianwei Yang, Lijun Zhou, Xiaoyang Zeng
A low-cost SoC implementation of AES algorithm for bio-signals. ASICON (2015)
Weizhen Wang, Jun Han, Jielin Wang, Xiaoyang Zeng
A SIMD multiplier-accumulator design for pairing cryptography. ASICON (2015)
Jielin Wang, Weizhen Wang, Jianwei Yang, Zhiyi Yu, Jun Han, Xiaoyang Zeng
Parallel implementation of AES on 2.5D multicore platform with hardware and software co-design. ASICON (2015)
Yi Ren, Jun Han, Zhiyi Yu, Sizhong Xuan, Xiaoyang Zeng
A lifting-based 2-D discrete wavelet transform architecture for data compression of bio-potential signals. ASICON (2015)
Shudong Tian, Jun Han, Jianwei Yang, Lijun Zhou, Xiaoyang Zeng
Motion artifact removal based on ICA for ambulatory ECG monitoring. ASICON (2015)
Gaowei Xu, Jun Han, Yao Zou, Xiaoyang Zeng
A 1.5-D Multi-Channel EEG Compression Algorithm Based on NLSPIHT. IEEE Signal Process. Lett. 22 (8) (2015)
Tianchan Guan, Jun Han, Xiaoyang Zeng
Exploration for energy-efficient ECC decoder of WBAN. ASICON (2015)
Sizhong Xuan, Jun Han, Zhiyi Yu, Yi Ren, Xiaoyang Zeng
A configurable SoC design for information security. ASICON (2015)
Jun Han, Yang Li, Zhiyi Yu, Xiaoyang Zeng
A 65 nm Cryptographic Processor for High Speed Pairing Computation. IEEE Trans. Very Large Scale Integr. Syst. 23 (4) (2015)
Jun Han, Renfeng Dou, Lingyun Zeng, Shuai Wang, Zhiyi Yu, Xiaoyang Zeng
A Heterogeneous Multicore Crypto-Processor With Flexible Long-Word-Length Computation. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2015)
Mengyuan Chen, Jun Han, Yicheng Zhang, Yao Zou, Yi Li, Xiaoyang Zeng
An error-resilient wavelet-based ECG processor under voltage overscaling. BioCAS (2014)
Zhiyi Yu, Ruijin Xiao, Kaidi You, Heng Quan, Peng Ou, Zheng Yu, Maofei He, Jiajie Zhang, Yan Ying, Haofan Yang, Jun Han, Xu Cheng, Zhang Zhang, Ming-e Jing, Xiaoyang Zeng
A 16-Core Processor With Shared-Memory and Message-Passing Communications. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2014)
Renfeng Dou, Jun Han, Yifan Bo, Zhiyi Yu, Xiaoyang Zeng
An Efficient Implementation of Montgomery Multiplication on Multicore Platform With Optimized Algorithm, Task Partitioning, and Network Architecture. IEEE Trans. Very Large Scale Integr. Syst. 22 (11) (2014)
Yi Li, Liang Wen, Yuejun Zhang, Xu Cheng, Jun Han, Zhiyi Yu, Xiaoyang Zeng
An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing. IEICE Electron. Express 11 (3) (2014)
Yao Zou, Jun Han, Xinqian Weng, Xiaoyang Zeng
An Ultra-Low Power QRS Complex Detection Algorithm Based on Down-Sampling Wavelet Transform. IEEE Signal Process. Lett. 20 (5) (2013)
Tianchan Guan, Jun Han, Xiaoyang Zeng
Highly flexible WBAN transmit-receive system based on USRP. ASICON (2013)
Gaowei Xu, Yao Zou, Jun Han, Xiaoyang Zeng
Low power design for FIR filter. ASICON (2013)
Mengyuan Chen, Jun Han, Dabin Fang, Yao Zou, Xiaoyang Zeng
An ultra low-power and area-efficient baseband processor for WBAN transmitter. APSIPA (2013)
Dabin Fang, Huikai Li, Jun Han, Xiaoyang Zeng
Robustness Analysis of Mesh-Based Network-on-Chip Architecture under Flooding-Based Denial of Service Attacks. NAS (2013)
Jun Han, Shuai Wang, Wei Huang, Zhiyi Yu, Xiaoyang Zeng
Parallelization of Radix-2 Montgomery Multiplication on Multicore Platform. IEEE Trans. Very Large Scale Integr. Syst. 21 (12) (2013)
Yi Li, Xu Cheng, Yicheng Zhang, Weijing Shi, Jun Han, Xiaoyang Zeng
A highly energy-efficient compressed sensing encoder with robust subthreshold clockless pipeline for wireless BANs. BioCAS (2013)
Weijing Shi, Yi Li, Jun Han, Xu Cheng, Xiaoyang Zeng
An extensible and real-time compressive sensing reconstruction hardware for WBANs using OMP. ASICON (2013)
Shuai Wang, Jun Han, Yang Li, Yifan Bo, Xiaoyang Zeng
A 920MHz quad-core cryptography processor accelerating parallel task processing of public-key algorithms. CICC (2013)
Yifan Bo, Renfeng Dou, Jun Han, Xiaoyang Zeng
A hardware-efficient variable-length FFT processor for low-power applications. APSIPA (2013)
Renfeng Dou, Yifan Bo, Jun Han, Xiaoyang Zeng
Design of a high throughput configurable variable-length FFT processor based on switch network architecture. ASICON (2013)
Pengjun Wang, Yuejun Zhang, Jun Han, Zhiyi Yu, Yibo Fan, Zhang Zhang
Architecture and Physical Implementation of Reconfigurable Multi-Port Physical Unclonable Functions in 65 nm CMOS. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (5) (2013)
Jun Han, Xingxing Zhang, Yi Li, Baoyu Xiong, Yuejun Zhang, Zhang Zhang, Zhiyi Yu, Xu Cheng, Xiaoyang Zeng
A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS. IEICE Electron. Express 9 (16) (2012)
Yifan Bo, Jun Han, Yao Zou, Xiaoyang Zeng
A low power ASIP for precision configurable FFT processing. APSIPA (2012)
Yuli Zhang, Jun Han, Xinqian Weng, Zhongzhu He, Xiaoyang Zeng
Design Approach and Implementation of Application Specific Instruction Set Processor for SHA-3 BLAKE Algorithm. IEICE Trans. Electron. (8) (2012)
Weina Zhou, Lin Dai, Yao Zou, Xiaoyang Zeng, Jun Han
A High Speed Reconfigurable Face Detection Architecture Based on AdaBoost Cascade Algorithm. IEICE Trans. Inf. Syst. (2) (2012)
Yang Li, Jun Han, Shuai Wang, Junbao Liu, Xiaoyang Zeng
A NoC-based multi-core architecture for IEEE 802.11i CCMP. ASICON (2011)
Shuai Wang, Yang Li, Junbao Liu, Jun Han, Xiaoyang Zeng
A security processor based on MIPS 4KE architecture. ASICON (2011)

Jun Han.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Jun Han