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A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS.
Jun Han
Xingxing Zhang
Yi Li
Baoyu Xiong
Yuejun Zhang
Zhang Zhang
Zhiyi Yu
Xu Cheng
Xiaoyang Zeng
Published in:
IEICE Electron. Express (2012)
Keyphrases
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low power
read write
power consumption
cmos technology
high speed
nm technology
low cost
single chip
vlsi circuits
low power consumption
image sensor
low voltage
mixed signal
power dissipation
delay insensitive
real time
flash memory
ultra low power
digital signal processing
parallel processing
video sequences