Xu Cheng

Publication Activity (10 Years)

Years Active: 2011-2024
Publications (10 Years): 30

Top Topics

Hierarchically Structured

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Circuits Syst. II Express Briefs

Microelectron. J.

Publications

Jiawei Wang, Zhao Gao, Xu Cheng, Jue Wang, Zhen Li, Jun Han, Xiaoyang Zeng
A 1.6 GS/s 42.6-dB SNDR Synthesis Friendly Time-Interleaved SAR ADC Using Metastability Detection and Escape Acceleration Technique. IEEE Trans. Circuits Syst. II Express Briefs 71 (4) (2024)
Zhen Li, Jing Wang, Man-Kay Law, Sijun Du, Junrui Liang, Xu Cheng, Jun Han, Xiaoyang Zeng, Zhiyuan Chen
Piezoelectric Energy Harvesting Interface Using Self-Bias-Flip Rectifier and Switched-PEH DC-DC for MPPT. IEEE J. Solid State Circuits 59 (7) (2024)
Yongliang Zhang, Yitong Rong, Xuyang Duan, Zhen Yang, Qiang Li, Ziyu Guo, Xu Cheng, Xiaoyang Zeng, Jun Han
An Energy-Efficient BNN Accelerator With Two-Stage Value Prediction for Sparse-Edge Gesture Recognition. IEEE Trans. Circuits Syst. I Regul. Pap. 71 (1) (2024)
Yuanyuan Han, Xu Cheng, Xiaoyong Xue, Jun Han, Jiawei Xu, Xiaoyang Zeng
SET Tolerable SRAM Hardened by DMR Circuit With Feedback-Split-Gate Voter and High-Speed Hierarchical Structure. IEEE Trans. Circuits Syst. II Express Briefs 71 (3) (2024)
Song Wang, Xu Cheng, Ziyu Guo, Jun Han
A foreground digital calibration algorithm for time-interleaved ADCs with low computational complexity. Microelectron. J. 136 (2023)
Baijie Zhang, Jiawei Wang, Xu Cheng, Jun Han, Xiaoyang Zeng
Dominant-Node Theory and Monitoring-Rescue Method for Eliminating Undesired Operating Points in the Self-Biased Reference Generators. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (12) (2023)
Yan Li, Chao Chen, Xu Cheng, Jun Han, Xiaoyang Zeng
DMBF: Design Metrics Balancing Framework for Soft-Error-Tolerant Digital Circuits Through Bayesian Optimization. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (10) (2023)
Yan Liu, Yan Li, Xu Cheng, Jun Han, Xiaoyang Zeng
A Non-Redundant Latch With Key-Node-Upset Obstacle of Beneficial Efficiency for Harsh Environments Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (4) (2023)
Zhen Li, Zhiyuan Chen, Man-Kay Law, Sijun Du, Xu Cheng, Xiaoyang Zeng, Jun Han
A Self Bias-flip Piezoelectric Energy Harvester Array without External Energy Reservoirs achieving 488% Improvement with 4-Ratio Switched-PEH DC-DC Converter. CICC (2023)
Jing Wang, Zhiyuan Chen, Junrui Liang, Xu Cheng, Jun Han, Xiaoyang Zeng
A Cross Regulation Reduced Multi-Output and Multi-VCR Piezoelectric Energy Harvesting System Using Shared Capacitors. ISCAS (2022)
Min Li, Jue Wang, Xu Cheng, Xiaoyang Zeng
A Fully Synthesizable Dynamic Latched Comparator with Reduced Kickback Noise. ISCAS (2022)
Jiawei Wang, Jue Wang, Xu Cheng, Jun Han, Xiaoyang Zeng
A Synthesis Friendly Dynamic Amplifier with Fuzzy-Logic Piecewise-Linear Calibration. ISCAS (2022)
Baijie Zhang, Jue Wang, Xu Cheng, Jun Han, Xiaoyang Zeng
An Enhanced Start-up Circuit Eliminating All Trojan States in Self-biased Reference Generators. ISCAS (2022)
Yong-Liang Zhang, Qiang Li, Hui Zhang, Wei-Zhen Wang, Jun Han, Xiaoyang Zeng, Xu Cheng
A 28 nm, 397 μW real-time dynamic gesture recognition chip based on RISC-V processor. Microelectron. J. 116 (2021)
Weizhen Wang, Jun Han, Xu Cheng, Xiaoyang Zeng
An energy-efficient crypto-extension design for RISC-V. Microelectron. J. 115 (2021)
Chiyu Tan, Yan Li, Xu Cheng, Jun Han, Xiaoyang Zeng
General Efficient TMR for Combinational Circuit Hardening Against Soft Errors and Improved Multi-Objective Optimization Framework. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (7) (2021)
Jue Wang, Xu Cheng, Jun Han, Xiaoyang Zeng
Synthesizable lead-lag quantization technique for digital VCO-based ΔΣ ADC. Microelectron. J. 110 (2021)
Jinrong Li, Jue Wang, Xu Cheng, Yicheng Zeng, Xiaoyang Zeng
A 0.9V Supply 12.5Gb/s LVDS Receiver in 28nm CMOS Process. ASICON (2021)
Jue Wang, Zhenyu Yang, Jiawei Wang, Xu Cheng, Jun Han, Xiaoyang Zeng
VCO-Based Delta Sigma Modulator with Digital Tri-level Feedback Scheme. A-SSCC (2021)
Yuanyuan Han, Tongde Li, Xu Cheng, Liang Wang, Jun Han, Yuanfu Zhao, Xiaoyang Zeng
Radiation Hardened 12T SRAM With Crossbar-Based Peripheral Circuit in 28nm CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (7) (2021)
Yan Li, Xu Cheng, Chiyu Tan, Jun Han, Yuanfu Zhao, Liang Wang, Tongde Li, Mehdi B. Tahoori, Xiaoyang Zeng
A Robust Hardened Latch Featuring Tolerance to Double-Node-Upset in 28nm CMOS for Spaceborne Application. IEEE Trans. Circuits Syst. II Express Briefs (9) (2020)
Xu Cheng, Jue Wang, Jun Han, Xiaoyang Zeng
Design Methodology of Clock Polarity Inversion Technique for Frequency Dividers. ISCAS (2020)
Jue Wang, Xu Cheng, Jun Han, Xiaoyang Zeng
A Synthesis Friendly VCO-Based Delta-Sigma ADC with Process Variation Tolerance. ISCAS (2020)
Guozhu Xin, Jun Han, Tianyu Yin, Yuchao Zhou, Jianwei Yang, Xu Cheng, Xiaoyang Zeng
VPQC: A Domain-Specific Vector Processor for Post-Quantum Cryptography Based on RISC-V Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2020)
Yuanyuan Han, Xu Cheng, Jun Han, Xiaoyang Zeng
Radiation-Hardened 0.3-0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications. IEEE Trans. Very Large Scale Integr. Syst. 28 (4) (2020)
Yan Li, Xiaoyoung Zeng, Zhengqi Gao, Liyu Lin, Jun Tao, Jun Han, Xu Cheng, Mehdi B. Tahoori, Xiaoyang Zeng
Exploring a Bayesian Optimization Framework Compatible with Digital Standard Flow for Soft-Error-Tolerant Circuit. DAC (2020)
Li Li, Xu Cheng, Zhang Zhang, Jianmin Zeng, Xiaoyang Zeng
A 24-bit sigma-delta ADC with configurable chopping scheme. IEICE Electron. Express 16 (10) (2019)
Xu Cheng, Xiaoyang Zeng, Qi Feng
Analysis and improvement of ramp gain error in single-ramp single-slope ADCs for CMOS image sensors. Microelectron. J. 58 (2016)
Liang Wen, Xu Cheng, Keji Zhou, Shudong Tian, Xiaoyang Zeng
Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier. IEEE Trans. Circuits Syst. II Express Briefs (7) (2016)
Liang Wen, Xu Cheng, Shudong Tian, Haibo Wen, Xiaoyang Zeng
Subthreshold Level Shifter With Self-Controlled Current Limiter by Detecting Output Error. IEEE Trans. Circuits Syst. II Express Briefs (4) (2016)
Xiaoyang Zeng, Yi Li, Yuejun Zhang, Shujie Tan, Jun Han, Xingxing Zhang, Zhang Zhang, Xu Cheng, Zhiyi Yu
Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process. IEEE Trans. Very Large Scale Integr. Syst. 23 (7) (2015)
Yawei Guo, Yue Wu, Dongdong Guo, Xu Cheng, Zhiyi Yu, Xiaoyang Zeng
Non-binary digital calibration for split-capacitor DAC in SAR ADC. IEICE Electron. Express 12 (4) (2015)
Zhiyi Yu, Ruijin Xiao, Kaidi You, Heng Quan, Peng Ou, Zheng Yu, Maofei He, Jiajie Zhang, Yan Ying, Haofan Yang, Jun Han, Xu Cheng, Zhang Zhang, Ming-e Jing, Xiaoyang Zeng
A 16-Core Processor With Shared-Memory and Message-Passing Communications. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2014)
Yi Li, Liang Wen, Yuejun Zhang, Xu Cheng, Jun Han, Zhiyi Yu, Xiaoyang Zeng
An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing. IEICE Electron. Express 11 (3) (2014)
Yue Wu, Xu Cheng, Xiaoyang Zeng
A split-capacitor vcm-based capacitor-switching scheme for low-power SAR ADCs. ISCAS (2013)
Biao Wang, Meng Zhang, Xu Cheng, Qi Feng, Xiaoyang Zeng
A 1.8-V 14-bit inverter-based incremental ΣΔ ADC for CMOS image sensor. ASICON (2013)
Yi Li, Xu Cheng, Yicheng Zhang, Weijing Shi, Jun Han, Xiaoyang Zeng
A highly energy-efficient compressed sensing encoder with robust subthreshold clockless pipeline for wireless BANs. BioCAS (2013)
Weijing Shi, Yi Li, Jun Han, Xu Cheng, Xiaoyang Zeng
An extensible and real-time compressive sensing reconstruction hardware for WBANs using OMP. ASICON (2013)
Yue Wu, Xu Cheng, Xiaoyang Zeng
A 960 μW 10-bit 70-MS/s SAR ADC with an energy-efficient capacitor-switching scheme. Microelectron. J. 44 (12) (2013)
Jun Han, Xingxing Zhang, Yi Li, Baoyu Xiong, Yuejun Zhang, Zhang Zhang, Zhiyi Yu, Xu Cheng, Xiaoyang Zeng
A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS. IEICE Electron. Express 9 (16) (2012)
Zhang Zhang, Zhiyi Yu, Xu Cheng, Xiaoyang Zeng
A low power 1.0 GHz VCO in 65nm-CMOS LP-process. ASICON (2011)
Jun Ma, Yawei Guo, Li Li, Yue Wu, Xu Cheng, Xiaoyang Zeng
A low power 10-bit 100-MS/s SAR ADC in 65nm CMOS. ASICON (2011)
Li Li, Jun Ma, Yawei Guo, Xu Cheng, Xiaoyang Zeng
A multi-mode 1-V DAC+filter in 65-nm CMOS for reconfigurable (GSM, TD-SCDMA and WCDMA) transmitters. ASICON (2011)
Hong Chang, Wenxian Lu, Xu Cheng, Yawei Guo, Xiaoyang Zeng
Modeling of a double-sampling switched-capacitor bandpass delta-sigma modulator for multi-standard applications. ASICON (2011)