Yan Li

Publication Activity (10 Years)

Years Active: 2020-2024
Publications (10 Years): 7

Top Topics

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Circuits Syst. II Express Briefs

Microelectron. J.

Publications

Chenyu Zhang, Yan Li, Wenfa Zhan, Wenping Geng, Ting Liang, Xiaoyang Zeng
Examining the role of tap cell in suppressing single event transient effect in 28-nm CMOS technology. Microelectron. J. 143 (2024)
Yan Li, Chao Chen, Xu Cheng, Jun Han, Xiaoyang Zeng
DMBF: Design Metrics Balancing Framework for Soft-Error-Tolerant Digital Circuits Through Bayesian Optimization. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (10) (2023)
Yan Liu, Yan Li, Xu Cheng, Jun Han, Xiaoyang Zeng
A Non-Redundant Latch With Key-Node-Upset Obstacle of Beneficial Efficiency for Harsh Environments Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (4) (2023)
Chiyu Tan, Yan Li, Xu Cheng, Jun Han, Xiaoyang Zeng
General Efficient TMR for Combinational Circuit Hardening Against Soft Errors and Improved Multi-Objective Optimization Framework. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (7) (2021)
Yan Li, Jun Han, Xiaoyang Zeng, Mehdi B. Tahoori
TRIGON: A Single-phase-clocking Low Power Hardened Flip-Flop with Tolerance to Double-Node-Upset for Harsh Environments Applications. DATE (2021)
Yan Li, Xu Cheng, Chiyu Tan, Jun Han, Yuanfu Zhao, Liang Wang, Tongde Li, Mehdi B. Tahoori, Xiaoyang Zeng
A Robust Hardened Latch Featuring Tolerance to Double-Node-Upset in 28nm CMOS for Spaceborne Application. IEEE Trans. Circuits Syst. II Express Briefs (9) (2020)
Yan Li, Xiaoyoung Zeng, Zhengqi Gao, Liyu Lin, Jun Tao, Jun Han, Xu Cheng, Mehdi B. Tahoori, Xiaoyang Zeng
Exploring a Bayesian Optimization Framework Compatible with Digital Standard Flow for Soft-Error-Tolerant Circuit. DAC (2020)